2.5D integrated circuit

A 2.5D integrated circuit (2.5D IC) is an advanced packaging technique{{cite web | url=https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/ | title=Advanced Packaging }} that combines multiple integrated circuit dies in a single package{{Cite web |url=https://www.open-silicon.com/2-5d-technology/ |title=2.5D Technology |website=Open-silicon.com |access-date=July 21, 2020 |archive-date=August 5, 2020 |archive-url=https://web.archive.org/web/20200805080319/https://www.open-silicon.com/2-5d-technology/ |url-status=dead }} without stacking them into a three-dimensional integrated circuit (3D-IC) with through-silicon vias (TSVs). The term "2.5D" originated when 3D-ICs with TSVs were quite new and still very difficult. Chip designers realized that many of the advantages of 3D integration could be approximated by placing bare dies side by side on an interposer instead of stacking them vertically. If the pitch is very fine and the interconnect very short, the assembly can be packaged as a single component with better size, weight, and power characteristics than a comparable 2D circuit board assembly. This half-way 3D integration was facetiously named "2.5D" and the name stuck.{{Cite web |url=https://www.eetimes.com/2d-vs-2-5d-vs-3d-ics-101/ |title=2D vs. 2.5D vs. 3D ICs 101 |first=Max |last=Maxfield |date=April 8, 2012 |website=EE Times}}

Since then, 2.5D has proven to be far more than just "half-way to 3D."{{Cite web |url=https://www.eetimes.com/2-5d-ics-are-more-than-a-stepping-stone-to-3d-ics/ |title=2.5D ICs are more than a stepping stone to 3D ICs |first=Mike |last=Santarini |date=March 27, 2012 |website=EE Times}}{{cite news |last1=Hoa |first1=Sily |title=Integrated Circuits |url=https://www.icrfq.com/blog/The-Symbols-Of-Integrated-Circuits.html |access-date=16 May 2024}}

Some benefits:

  • An interposer can support heterogeneous integration – that is, dies of different pitch, size, material, and process node.{{Cite journal |url=http://adsabs.harvard.edu/abs/2015ApPRv...2b1308Z |title=Heterogeneous 2.5D integration on through silicon interposer |first1=Xiaowu |last1=Zhang |first2=Jong Kai |last2=Lin |first3=Sunil |last3=Wickramanayaka |first4=Songbai |last4=Zhang |first5=Roshan |last5=Weerasekera |first6=Rahul |last6=Dutta |first7=Ka Fai |last7=Chang |first8=King-Jien |last8=Chui |first9=Hong Yu |last9=Li |first10=David Soon |last10=Wee Ho |first11=Liang |last11=Ding |first12=Guruprasad |last12=Katti |first13=Suryanarayana |last13=Bhattacharya |first14=Dim-Lee |last14=Kwong |date=June 1, 2015 |journal=Applied Physics Reviews |volume=2 |issue=2 |pages=021308 |via=NASA ADS |doi=10.1063/1.4921463 |bibcode=2015ApPRv...2b1308Z}}
  • Placing dies side by side instead of stacking them reduces heat buildup.{{cite web |url=https://web.ece.ucsb.edu/~iakgun/files/ISVLSI2016.pdf |title=Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space |year=2016 |website=Department of Electrical and Computer Engineering, UC Santa Barbara |access-date=October 20, 2020}}
  • Upgrading or modifying a 2.5D assembly is as easy as swapping in a new component and revamping the interposer to suit; much faster and simpler than reworking an entire 3D-IC or System-on-Chip (SoC).

Some sophisticated 2.5D assemblies even incorporate TSVs and 3D components. Several foundries now support 2.5D packaging.{{Cite web |url=https://www.intel.com/content/www/us/en/foundry/emib.html |title=Intel Custom Foundry EMIB |website=Intel Corporation |url-status=dead |archive-url=https://web.archive.org/web/20150713230215/https://www.intel.com/content/www/us/en/foundry/emib.html |archive-date=July 13, 2015}}{{Cite web |url=https://nhanced-semi.com/technology/about-2-5d-technology/ |title=About 2.5D Technology |website=NHanced Semiconductors, Inc. |date=March 23, 2017}}{{Cite web |url=https://www.marvell.com/products/custom-asic.html |title=Custom ASICs |website=Marvell.com}}{{Cite web |url=https://www.electronicdesign.com/technologies/digital-ics/article/21801569/qa-a-deeper-look-at-marvells-mochi-technology |title=Q&A: A Deeper Look at Marvell's MoChi Technology |first=William G. |last=Wong |date=June 6, 2016 |website=Electronicdesign.com}}{{Cite web |url=https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm |title=What is SoIC? |website=Taiwan Semiconductor Manufacturing Company Ltd}}

The success of 2.5D assembly has given rise to "chiplets" – small, functional circuit blocks designed to be combined in mix-and-match fashion on interposers. Several high-end products{{cite web |url=https://www.amd.com/en/partner/elite-performance-ryzen-3000xt-processors |title=Elite Performance with AMD Ryzen 3000XT Series Processors |website=AMD.com |access-date=October 20, 2020}}{{Cite web |url=https://www.marvell.com/company/newsroom/marvell-introduces-industrys-first-hyper-scale-quad-arm-cortex-a72-and-dual-cortex-a53-based-chips-on-marvells-revolutionary-mochi-and-flc-architecture.html |title=Marvell Introduces Industry's First Hyper-Scale Quad ARM Cortex-A72 and Dual Cortex-A53 Based Chips on Marvell's Revolutionary MoChi and FLC Architecture |date=October 6, 2015 |website=Marvell.com}} already take advantage of these LEGO-style chiplets; some experts predict{{Cite web |url=https://spectrum.ieee.org/intels-view-of-the-chiplet-revolution |title=Intel's View of the Chiplet Revolution |first=Samuel K. |last=Moore |date=April 12, 2019 |website=IEEE Spectrum: Technology, Engineering, and Science News}} the emergence of an industry-wide chiplet ecosystem. Interposers can be larger than the reticle size which is the maximum area that can be projected by a photolithography scanner or stepper.

{{cite web | url=https://fuse.wikichip.org/news/3377/tsmc-announces-2x-reticle-cowos-for-next-gen-5nm-hpc-applications/ | title=TSMC Announces 2x Reticle CoWoS for Next-Gen 5nm HPC Applications | date=3 March 2020 }}

References