256-bit computing

A 256-bit quantity can store 2²⁵⁶ different values. The range of integer values that can be stored in 256 bits depends on the integer representation used.

The range of a signed 256-bit integer is from {{zwsp|−57,|896,|044,|618,|658,|097,|711,|785,|492,|504,|343,|953,|926,|634,|992,|332,|820,|282,|019,|728,|792,|003,|956,|564,|819,|968}} to {{zwsp|57,|896,|044,|618,|658,|097,|711,|785,|492,|504,|343,|953,|926,|634,|992,|332,|820,|282,|019,|728,|792,|003,|956,|564,|819,967}}.

256-bit processors could be used for addressing directly up to 2²⁵⁶ bytes. Already 2¹²⁸ (for 128-bit addressing) would greatly exceed the total data stored on Earth as of 2018, which has been estimated to be around 33.3 ZBs (over 2⁷⁴ bytes).{{cite book |last1=Reinsel |first1=David |last2=Gantz |first2=John |last3=Rydning |first3=John |title=The Digitization of the World |date=November 2018 |publisher=IDC |page=6 |url=https://www.seagate.com/files/www-content/our-story/trends/files/idc-seagate-dataage-whitepaper.pdf |access-date=27 October 2022}}

Xbox 360 was the first high-definition gaming console to utilize the ATI Technologies 256-bit GPU Xenos{{cite web | url=https://www.cnet.com/reviews/xbox-360-review/ | title=Xbox 360 review: Xbox 360 | date=February 15, 2006 | website=CNET}} before the introduction of the current gaming consoles especially Nintendo Switch.

Some buses on the newer System on a chip (e.g. Tegra developed by Nvidia) utilize 64-bit, 128-bit, 256-bit, or higher.

File:Sharp PC-MM2 frontal view.jpg processor]]

CPUs feature SIMD instruction sets (Advanced Vector Extensions and the FMA instruction set etc.) where 256-bit vector registers are used to store several smaller numbers, such as eight 32-bit floating-point numbers, and a single instruction can operate on all these values in parallel. However, these processors do not operate on individual numbers that are 256 binary digits in length, only their registers have the size of 256-bits. Binary digits are found together in 128-bit collections.

Modern GPU chips may operate data across a 256-bit memory bus (or possibly a 512-bit bus with HBM3{{Cite web|first=Scharon |last=Harding |date=15 April 2021|title=What Are HBM, HBM2 and HBM2E? A Basic Definition|url=https://www.tomshardware.com/reviews/glossary-hbm-hbm2-high-bandwidth-memory-definition,5889.html|access-date=2021-09-11|website=Tom's Hardware|language=en}}).

The Efficeon processor was Transmeta's second-generation 256-bit VLIW design which employed a software engine to convert code written for x86 processors to the native instruction set of the chip.{{Cite web|url=http://datasheets.chipdb.org/Transmeta/pdfs/brochures/efficeon_tm8300_processor.pdf|title=Transmeta Efficeon TM8300 Processor|publisher=Transmeta Corporation|archive-url=https://web.archive.org/web/20190210132436/http://datasheets.chipdb.org/Transmeta/pdfs/brochures/efficeon_tm8300_processor.pdf|archive-date=10 February 2019|url-status=live}}{{Cite web|url=http://www.pcworld.com/article/101516/transmeta_unveils_plans_for_tm8000_processor.html|title=Transmeta Unveils Plans for TM8000 Processor|last=Williams|first=Martyn|date=29 May 2002|website=PC World|archive-url=https://web.archive.org/web/20100414160937/http://www.pcworld.com/article/101516/transmeta_unveils_plans_for_tm8000_processor.html|archive-date=14 April 2010|url-status=dead}}

The DARPA funded Data-Intensive Architecture (DIVA) system incorporated processor-in-memory (PIM) 5-stage pipelined 256-bit datapath, complete with register file and ALU blocks in a "WideWord" processor in 2002.{{Cite conference|last1=Draper|first1=Jeffrey|last2=Sondeen|first2=Jeff|last3=Chang Woo Kang|date=October 2002|title=Implementation of a 256-bit WideWord Processor for the Data-Intensive Architecture (DIVA) Processing-In-Memory (PIM) Chip|url=http://sportlab.usc.edu/~changk/publications/esscirc02.pdf|url-status=live|conference=International Solid-State Circuits Conference|archive-url=https://web.archive.org/web/20170829201228/http://sportlab.usc.edu/~changk/publications/esscirc02.pdf|archive-date=29 August 2017}}

• 256 bits is a common key size for symmetric ciphers in cryptography, such as Advanced Encryption Standard (AES).
• Increasing the word size can accelerate multiple precision mathematical libraries. Applications include cryptography.
• Researchers at the University of Cambridge use a 256-bit capability pointer, which includes capability and addressing information, on early implementations of their CHERI capability system.{{cite web|url=http://www.csl.sri.com/users/neumann/2012resolve-cheri.pdf|title=CHERI: a research platform deconflating hardware virtualization and protection|last1=Watson|first1=Robert N. M.|author-link=Robert Watson (computer scientist)|last2=Neumann|first2=Peter G.|author2-link=Peter G. Neumann|date=3 March 2012|work=Unpublished workshop paper for RESoLVE’12, March 3, 2012, London, UK|publisher=SRI International Computer Science Laboratory|last3=Woodruff|first3=Jonathan|last4=Anderson|first4=Jonathan|last5=Anderson|first5=Ross|author-link5=Ross J. Anderson|last6=Dave|first6=Nirav|last7=Laurie|first7=Ben|author-link7=Ben Laurie|last8=Moore|first8=Simon W.|last9=Murdoch|first9=Steven J.|author-link9=Steven Murdoch|first10=Philip|last10=Paeps|first11=Michael|last11=Roe|first12=Hassen|last12=Saidi}}
• SHA-256 hash function.
• Smart contracts use 256- or 257-bit integers; 256-bit words for the Ethereum Virtual Machine. "We realize that a 257 bits byte is quite unusual, but for smart contracts it is ok to have at least 256 bits numbers. The leading VM for smart contracts, Ethereum VM, introduced this practice and other blockchain VMs followed."{{Cite web|first=Dmitriy |last=Borisenkov |date=23 October 2019|title=[llvm-dev] RFC: On non 8-bit bytes and the target for it|url=https://lists.llvm.org/pipermail/llvm-dev/2019-October/136115.html|access-date=2021-09-11}}
• The Zig programming language has built-in support for signed and unsigned arbitrary bit-width integers for all supported platforms, including 256-bit.{{Cite web|title=Primitive Types|url=https://ziglang.org/documentation/master/#Primitive-Types|access-date=2024-07-05|website=ziglang.org}} The calling convention for exported functions using such integers however, has not been specified in ABIs.

• Berkeley IRAM project
• Computational RAM

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Category:Data unit