ARM11

{{See also|ARM architecture|List of ARM cores}}

The ARM11 product family (announced 29 April 2002) introduced the ARMv6 architectural additions which had been announced in October 2001. These include SIMD media instructions, multiprocessor support, exclusive loads and stores instructions{{Cite web |url=https://documentation-service.arm.com/static/5e8e1e0388295d1e18d368b2 |title=ARM11 MPCore Processor Revision: r2p0 Technical Reference Manual |page=36(1-4),301-302(8-7,8-8) |accessdate=2023-12-14}} and a new cache architecture. The implementation included a significantly improved instruction processing pipeline, compared to previous ARM9 or ARM10 families, and is used in smartphones from Apple, Nokia, and others. The initial ARM11 core (ARM1136) was released to licensees in October 2002.

The ARM11 family are currently the only ARMv6-architecture cores. There are, however, ARMv6-M cores (Cortex-M0 and Cortex-M1), addressing microcontroller applications;not supported by Linux as of version 3.3 ARM11 cores target more demanding applications.

In terms of instruction set, ARM11 builds on the preceding ARM9 generation. It incorporates all ARM926EJ-S features {{Nintendo wii Starlet}} and adds the ARMv6 instructions for media support (SIMD) and accelerating IRQ response.

Microarchitecture improvements in ARM11 cores"The ARM11 Microarchitecture", ARM Ltd, 2002 include:

• SIMD instructions which can double MPEG-4 and audio digital signal processing algorithm speed
• Cache is physically addressed, solving many cache aliasing problems and reducing context switch overhead.
• Unaligned and mixed-endian data access is supported.
• Reduced heat production and lower overheating risk
• Redesigned pipeline, supporting faster clock speeds (target up to 1 GHz)
• Longer: 8 (vs 5) stages
• Out-of-order completion for some operations (e.g., stores)
• Dynamic branch prediction/folding (like XScale)
• Cache misses don't block execution of non-dependent instructions.
• Load/store parallelism
• ALU parallelism
• 64-bit data paths

JTAG debug support (for halting, stepping, breakpoints, and watchpoints) was simplified. The EmbeddedICE module was replaced with an interface which became part of the ARMv7 architecture. The hardware tracing modules (ETM and ETB) are compatible, but updated, versions of those used in the ARM9. In particular, trace semantics were updated to address parallel instruction execution and data transfers.

ARM makes an effort to promote recommended Verilog coding styles and techniques. This ensures semantically rigorous designs, preserving identical semantics throughout the chip design flow, which included extensive use of formal verification techniques. Without such attention, integrating an ARM11 with third-party designs could risk exposing hard-to-find latent bugs. Due to ARM cores being integrated into many different designs, using a variety of logic synthesis tools and chip manufacturing processes, the impact of its register-transfer level (RTL) quality is magnified many times.The Dangers of Living with an X (bugs hidden in your Verilog), Version 1.1 (14 October 2003). The ARM11 generation focused more on synthesis than previous generations, making such concerns more of an issue.

There are four ARM11 cores:

• ARM1136{{cite web|url=https://developer.arm.com/documentation/ddi0211/k/|title=ARM1136JF-S and ARM1136J-S Technical Reference Manual Revision: r1p5; ARM DDI 0211K}}
• ARM1156, introduced Thumb2 instructions
• ARM1176, introduced security extensions{{cite web|url=https://developer.arm.com/documentation/ddi0301/h/|title=ARM1176JZF-S Technical Reference Manual Revision: r0p7|access-date=4 October 2012}}
• ARM11MPcore, introduced multicore support

File:Raspberry Pi B+ top.jpg

File:KraftCom CoaxLine Adapter CN-KE502M - Atheros AR7400-AG2C-9835.jpg

File:Garmin Edge Explore - board - STMicroelectronics STA2065N2-1727.jpg STA2065N2 (ARM1176) with embedded GPS]]

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• Ambarella A5s, A7, A7L
• ASPEED Technology Inc. AST25xx
• Broadcom BCM2835 (Raspberry Pi 1 A/B, Pi Zero), BCM21553
• Cavium ECONA CNS3000 series{{cite press release|url=http://www.cavium.com/newsevents_Caviumnetworks_ECONA-CNS3XXX.html|title=Cavium Networks Introduces ECONA Family of Super Energy Efficient ARM-Based System-on-Chip (SoC) Processors for the Digital Home that break the 1 Watt Barrier|date=8 September 2009|publisher=Cavium|access-date=14 November 2015|archive-date=17 November 2015|archive-url=https://web.archive.org/web/20151117031603/http://www.cavium.com/newsevents_Caviumnetworks_ECONA-CNS3XXX.html|url-status=dead}}
• CSR Quatro 4230, 45xx, 53xx
• Freescale Semiconductor i.MX3x series, such as i.MX31, i.MX35
• Infotmic IMAPX2xx
• Nintendo CTR-CPU (Nintendo 3DS, New Nintendo 3DS)
• NTC Module 1879VYa1Ya, K1879KhB1Ya, 1879KhK1Ya, K1888VS018
• Nvidia Tegra
• MediaTek MT6276, MT6573
• Mindspeed Comcerto 1000 (Freescale LS102MA)
• Philips Semiconductor/NXP/ST-NXP Wireless Nomadik STn8820
• PLX Technology NAS782x
• Qualcomm MSM720x, MSM7x27
• Qualcomm Atheros AR7400
• Samsung S3C64xx, S5P64xx, S5L87xx, S5L89xx or Exynos Dual with Logic11
• Telechips TCC8902
• Texas Instruments OMAP2 series, with a TMS320 C55x or C64x DSP as a second core
• iPhone 3G series, with a Samsung ARM 1176JZ chip
• Xcometic KVM2800

{{Portal|Electronics}}

• ARM architecture
• Interrupt, Interrupt handler
• JTAG
• List of ARM architectures and cores
• Real-time operating system, Comparison of real-time operating systems

{{Reflist|30em}} BlackBerry Torch 9810

{{Commons category multi|ARM11}}

;ARM11 official documents

• {{Official website|http://www.arm.com/products/processors/classic/arm11/index.php|ARM11 official website}}
• Architecture Reference Manuals: [https://silver.arm.com/download/ARM_Architecture/AR550-DA-70002-r0p0-00rel0/DDI%2001001.pdf ARMv4/5/6], [https://silver.arm.com/download/ARM_and_AMBA_Architecture/AR570-DA-70000-r0p0-00rel2/DDI0406C_C_arm_architecture_reference_manual.pdf ARMv7-A/R]
• Core Reference Manuals: [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0211k/DDI0211K_arm1136_r1p5_trm.pdf ARM1136J(F)-S], [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0338g/DDI0338G_arm1156t2s_r0p4_trm.pdf ARM1156T2-S], [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0290g/DDI0290G_arm1156t2fs_r0p4_trm.pdf ARM1156T2F-S], [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0333h/DDI0333H_arm1176jzs_r0p7_trm.pdf ARM1176JZ-S], [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301h/DDI0301H_arm1176jzfs_r0p7_trm.pdf ARM1176JZF-S], [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0360f/DDI0360F_arm11_mpcore_r2p0_trm.pdf ARM11 MPCore]
• Coprocessor Reference Manual: [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0274h/DDI0274H_vfp11_r1p5_trm.pdf VFP11 (Floating-Point for ARM1136JF-S)]

;Quick Reference Cards

• Instructions: Thumb ([http://infocenter.arm.com/help/topic/com.arm.doc.qrc0006e/QRC0006_UAL16.pdf 1]), ARM and Thumb-2 ([http://infocenter.arm.com/help/topic/com.arm.doc.qrc0001m/QRC0001_UAL.pdf 2]), Vector Floating Point ([http://infocenter.arm.com/help/topic/com.arm.doc.qrc0007e/QRC0007_VFP.pdf 3])
• Opcodes: Thumb ([http://re-eject.gbadev.org/files/ThumbRefV2-beta.pdf 1], [http://www.mechcore.net/files/docs/ThumbRefV2-beta.pdf 2]), ARM ([http://re-eject.gbadev.org/files/armref.pdf 3], [http://www.mechcore.net/files/docs/armref.pdf 4]), GNU Assembler Directives [http://re-eject.gbadev.org/files/GasARMRef.pdf 5].

;Other

• [http://wanderingcoder.net/2010/07/19/ought-arm/ ARM11 lacks an integer hardware division instruction] {{Webarchive|url=https://web.archive.org/web/20200704000617/http://wanderingcoder.net/2010/07/19/ought-arm/ |date=4 July 2020 }}
• [http://www.cs.virginia.edu/~skadron/cs433_s09_processors/arm11.pdf The ARM11 Architecture], 2009, by Ian Davey and Payton Oliveri

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{{Classic ARM-based chips|state=expanded}}

{{Application ARM-based chips}}

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Category:ARM processors

Category:32-bit microprocessors