C-element

For two input signals the C-element is defined by the equation $y\_n=x\_1x\_2+(x\_1+x\_2)y\_\{n-1\}$, which corresponds to the following truth table:

This table can be turned into a circuit using the Karnaugh map. However, the obtained implementation is naive, since nothing is said about delay assumptions. To understand under what conditions the obtained circuit is workable, it is necessary to do additional analysis, which reveals that

• delay1 is a propagation delay from node 1 via environment to node 3,
• delay2 is a propagation delay from node 1 via internal feedback to node 3,
• delay1 must be greater than delay2.

Thus, the naive implementation is correct only for slow environment.J. Cortadella, M. Kishinevsky, [https://www.inf.pucrs.br/~calazans/graduate/SSD/Tutorial_Cortadella_Lyngby_Summer_School_1997.pdf Tutorial: Synthesis of control circuits from STG specifications]. Summer school, Lyngby, 1997.

Depending on the requirements to the switching speed and power consumption, the C-element can be realized as a coarse- or fine-grain circuit. Also, one should distinguish between single-output and dual-railA. Mokhov, V. Khomenko, D. Sokolov and A. Yakovlev, [http://async.org.uk/tech-reports/NCL-EECE-MSD-TR-2010-162.pdf "On dual-rail control logic for enhanced circuit robustness"], IEEE Int. Conference on Application of Concurrency to System Design (ACSD) 2012, pp. 112–121. realizations of C-element. A dual-rail C-element can be realized on 2-input NANDs (NORs) only.[https://www.researchgate.net/profile/Vuacheslav-Marakhovsky/publication/265767101_Functional_completeness_in_the_class_of_semimodular_circuits/links/54dfbec00cf2953c22b42dd7/Functional-completeness-in-the-class-of-semimodular-circuits.pdf V. Varshavskiy, M. Kishinevskiy, V. Marakhovskiy, L. Rozenblyum, "Functional completeness in the class of semimodular circuits," Soviet Journal of Computer and Systems Sciences, vol. 23, no. 6, pp. 70-80, 1985.] A single-output realization is workable if and only if:B. S. Tsirlin, "A Survey of Equivalent Problems of Realizing Circuits in the AND-NOT Basis that are Speed-Independent", Soviet Journal of Computer and Systems Sciences, vol. 24, 1986, pp. 58–69 (Б. С. Цирлин, [http://www.ee.bgu.ac.il/~kushnero/asynchronous/Varshavsky%20and%20Co/Tsirlin/Tsirlin_Review%20of%20realization%20problems%20in%20NAND%20basis.pdf "Обзор эквивалентных проблем реализации схем в базисе И-НЕ, не зависящих от скорости"], Изв. АН СССР, Техническая кибернетика, №2, 1986, с. 159–171).

1. The circuit, where each input of a C-element is connected through a separate inverter to its output, is semimodular relatively to the state, where all the inverters are excited.
2. This state is live for the output gate of C-element.

Image:Single_gate_C_elements.png

Image:Semistatic_C-elements.png

In his report Muller proposed to realize C-element as a majority gate with feedback. However, to avoid hazards linked with skews of internal delays, the majority gate must have as small number of transistors as possible.D. Hampel, K. Prost, and N. Scheingberg, [http://worldwide.espacenet.com/publicationDetails/originalDocument?CC=US&NR=3900742A&KC=A&FT=D&ND=3&date=19750819&DB=EPODOC&locale=en_EP "Threshold logic using complementary MOS device"], Patent US3900742, Aug. 19, 1975.D. Doman, [http://samples.sainsburysebooks.co.uk/9781118273111_sample_406813.pdf Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon] {{Webarchive|url=https://web.archive.org/web/20151008213805/http://samples.sainsburysebooks.co.uk/9781118273111_sample_406813.pdf |date=2015-10-08 }}. Wiley, 2012, 327 p. Generally, C-elements with different timing assumptionsK. S. Stevens, R. Ginosar and S. Rotem, [http://webee.technion.ac.il/~ran/papers/TVLSI-RelativeTiming-2002.pdf "Relative timing [asynchronous design]"], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 1, pp. 129–140, 2003. can be built on AND-OR-Invert (AOI)H. Zemanek, [http://www.degruyter.com/view/j/itit.1962.4.issue-1-6/itit.1962.4.16.248/itit.1962.4.16.248.xml "Sequentielle asynchrone Logik"], Elektronische Rechenanlagen, vol. 4, no. 6, pp. 248–253, 1962. Also available in Russian as Г. Цеманек, [http://www.ee.bgu.ac.il/~kushnero/asynchronous/Zemanek.pdf "Последовательная асинхронная логика"], Mеждународный симпозиум ИФАК Теория конечных и вероятностных автоматов 1962, с. 232—245.W. Fleischhammer, [http://worldwide.espacenet.com/publicationDetails/originalDocument?CC=GB&NR=1199698A&KC=A&FT=D&ND=8&date=19700722&DB=EPODOC&locale=en_EP "Improvements in or relating to asynchronous bistable trigger circuits"], UK patent specification GB1199698, Jul. 22, 1970. or its dual, OR-AND-Invert (OAI) gateT.-Y. Wuu and S. B. K. Vrudhula, [https://ieeexplore.ieee.org/document/238414/ "A design of a fast and area efficient multi-input Muller C-element"], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 2, pp. 215–219, 1993.H. K. O. Berge, A. Hasanbegovic, S. Aunet, [https://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5783079 "Muller C-elements based on minority-3 functions for ultra low voltage supplies"], IEEE Int. Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) 2011, pp. 195–200. and inverter. Yet another option patented by Varshavsky et al.V. I. Varshavsky, A. Y. Kondratyev, N. M. Kravchenko, and B. S. Tsirlin, [https://worldwide.espacenet.com/publicationDetails/originalDocument?CC=SU&NR=1411934A1&KC=A1&FT=D&ND=3&date=19880723&DB=EPODOC&locale=en_EP "H flip-flop"], USSR Author's certificate SU1411934 Jul. 23, 1988.

V. I. Varshavsky, N. M. Kravchenko, V. B. Marakhovsky and B. S. Tsirlin, [https://worldwide.espacenet.com/publicationDetails/originalDocument?CC=SU&NR=1443137A1&KC=A1&FT=D&ND=3&date=19881207&DB=EPODOC&locale=en_EP "H flip-flop"], USSR Author's certificate SU1443137, Dec. 7, 1988. is to shunt the input signals when they are not equal each other. Being very simple, these realizations dissipate more power due to the short-circuits. Connecting an additional majority gate to the inverted output of C-element, we obtain inclusive OR (EDLINCOR) function:{{cite journal | url=https://doi.org/10.1049/ip-e.1993.0018 | doi=10.1049/ip-e.1993.0018 | title=Event-driven logic (EDL) approach to digital systems representation and related design processes | date=1993 | last1=Pucknell | first1=D.A. | journal=IEE Proceedings E - Computers and Digital Techniques | volume=140 | issue=2 | pages=119–126 }}A. Yakovlev, M. Kishinevsky, A. Kondratyev, L. Lavagno, M. Pietkiewicz-Koutny, [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.19.4630&rep=rep1&type=pdf "On the models for asynchronous circuit behaviour with OR causality"], Formal Methods in System Design, vol. 9, no. 3, pp. 189—233. 1996. $z\_n\; =\; x\_1\; x\_2\; +\; (x\_1\; +\; x\_2)\; \backslash overline\{y\_n\}$. Some simple asynchronous circuits like pulse distributorsJ. C. Nelson, [https://archive.org/stream/speedindependent71nels#page/n5/mode/2up Speed-independent counting circuits]. Report no. 71, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1956. can be built solely on majority gates.

Semistatic C-element stores its previous state using two cross-coupled inverters, similar to an SRAM cell. One of the inverters is weaker than the rest of the circuit, so it can be overpowered by the pull-up and pull-down networks. If both inputs are 0, then the pull-up network changes the latch's state, and the C-element outputs a 0. If both inputs are 1, then the pull-down network changes the latch's state, making the C-element output a 1. Otherwise, the input of the latch is not connected to either $V\_\backslash text\{dd\}$ or ground, and so the weak inverter dominates and the latch outputs its previous state. There are also versions of semistatic C-element built on devices with negative differential resistance (NDR).C.-H. Lin, K. Yang, A. F. Gonzalez, J. R. East, P. Mazumder, G. I. Haddad, [https://ieeexplore.ieee.org/document/773722/ "InP-based high speed digital logic gates using an RTD/HBT heterostructure"], Int. Conference on Indium Phosphide and Related Materials (IPRM) 1999, pp. 419–422.{{cite book | chapter-url=https://ieeexplore.ieee.org/document/1137684 | doi=10.1109/SBCCI.2002.1137684 | chapter=Asynchronous circuit design based on the RTBT monostable-bistable logic transition element (MOBILE) | title=Proceedings. 15th Symposium on Integrated Circuits and Systems Design | date=2002 | last1=Glosekotter | first1=P. | last2=Pacha | first2=C. | last3=Goser | first3=K.F. | last4=Prost | first4=W. | last5=Kim | first5=S. | last6=Van Husen | first6=H. | last7=Reimann | first7=T. | last8=Tegude | first8=F.J. | pages=365–370 | isbn=0-7695-1807-9 }} NDR is usually defined for small signal, so it is difficult to expect that such a C-element will operate in full range of voltages or currents.{{original research inline|date=March 2020}}

Image:Realizations_of_C_element.png

Image:Dual-rail C-element.png

Image:David cell graph.png

There is a number of different single-output circuits of C-element built on logic gates.B. S. Tsirlin, [https://patentimages.storage.googleapis.com/bd/d8/4b/81b12c002a0615/SU1096759A1.pdf "H flip-flop"], USSR author's certificate SU1096759, Jun. 7, 1984.B. S. Tsirlin, [https://patentimages.storage.googleapis.com/b1/bf/92/42303ee73cf5ac/SU1162019A1.pdf "Multiple input H flip-flop"], USSR author's certificate SU1162019, Jun. 15, 1985. In particular, the so-called Maevsky's implementation M. Kuwako, T. Nanya, [https://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=656283 "Timing-reliability evaluation of asynchronous circuits based on different delay models"], IEEE Int. Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC) 1994, pp. 22–31.{{cite book | chapter-url=https://ieeexplore.ieee.org/document/514652 | doi=10.1109/WCADM.1995.514652 | chapter=Testing C-elements is not elementary | title=Proceedings Second Working Conference on Asynchronous Design Methodologies | date=1995 | last1=Brzozowski | first1=J.A. | last2=Raahemifar | first2=K. | pages=150–159 | isbn=0-8186-7098-3 }}P. A. Beerel, J. R. Burch, T. H. Meng, [https://link.springer.com/article/10.1023/A:1008666605437 "Checking combinational equivalence of speed-independent circuits"], Formal Methods in System Design, vol. 13, no. 1, 1998, pp. 37–85. is a semimodular, but non-distributive (OR-causal) circuit loosely based on.V. I. Varshavsky, O. V. Maevsky, Yu. V. Mamrukov, B. S. Tsirlin, [https://patentimages.storage.googleapis.com/fb/81/d2/fa3a9d86aa6917/SU1081801A1.pdf "H flip-flop"], USSR author's certificate SU1081801, Mar. 23, 1984 The NAND3 gate in this circuit can be replaced by two NAND2 gates. Note that Maevsky's C-element is actually a Join element, whose input signals cannot switch twice. Yet another circuit with OR-causality, which operates as a Join element.G. S. Brailovsky, L. Ya. Rozenblyum, B. S. Tsirlin, [https://patentimages.storage.googleapis.com/41/1a/f8/394838c3c7d619/SU1432733A1.pdf "H-flip-flop"], USSR author's certificate SU1432733, Oct. 23, 1988. A realization of C-element on two-input gates only has been proposed by Tsirlin B. S. Tsirlin, [https://patentimages.storage.googleapis.com/d0/78/f9/43bc147866ddb5/SU1324106A1.pdf "H-flip-flop"], USSR author's certificate SU1324106, Jul. 15, 1987. and then synthesized by Starodoubtsev et al. using Taxogram languageN. A. Starodoubtsev, S. A. Bystrov, [https://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1354042&matchBoolean=true&searchWithin%5B%5D=%22Last+Name%22%3Astarodoubtsev&newsearch=true "Monotonic behavior refinement for synthesis of two-input-gate asynchronous circuits"], IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2004, vol. I, pp. I-521–524. This circuit coincides with that attributed to Bartky

, and can operate without the input latch.

Note that both the Maevsky and Tsirlin circuits are based actually on so-called David cell.[https://web.archive.org/web/20170905042145/http://ieeexplore.ieee.org/document/4244956/ M. Courvoisier and P. Azema, "Asynchronous sequential machines with request/acknowledge operating mode," IEE Electronics Letters, Vol. 10, no. 1, pp.8-10, 1974.] Its fast transistor-level implementation is used in the semistatic C-element proposed.S. M. Fairbanks, [http://worldwide.espacenet.com/publicationDetails/originalDocument?CC=US&NR=6281707B1&KC=B1&FT=D&ND=3&date=20010828&DB=EPODOC&locale=en_EP "Two-stage Muller C-element"], United States Patent US6281707, Aug. 28, 2001. Yet another semistatic circuit using pass transistors (actually MUX 2:1) has been proposed.A. Morgenshtein, M. Moreinis, R. Ginosar, [http://webee.technion.ac.il/~ran/papers/Async-GDI-circuits-Nov02.pdf "Asynchronous gate-diffusion-input (GDI) circuits"], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 8, pp. 847–856, 2004. Yet another version of the C-element built on two SR-latches has been synthesized by MurphyJ. P. Murphy, [https://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6317230 "Design of latch-based C-element"], Electronics Letters, vol. 48, no. 19, 2012, pp. 1190–1191. using Petrify tool. However, this circuit includes inverter connected to one of the inputs. This inverter should have small delay. However, there are realizations of RS latches that already have one inverted input, for example.V. A. Maksimov and Ya. Ya. Petrichkovich [https://yandex.ru/patents/doc/SU1164867A1_19850630 "RS flip-flop,"] USSR author's certificate SU1164867, Jun. 30, 1985. Some speed-independent approachesP. Beerel and T. H.-Y. Meng. [http://dl.acm.org/citation.cfm?id=304171 "Automatic gate-level synthesis of speed-independent circuits"], IEEE/ACM Int. Conference on Computer-Aided Design (ICCAD) 1992, pp. 581–587.A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev, [http://dl.acm.org/citation.cfm?id=196275 "Basic gate implementation of speed-independent circuits"], ACM Design Automation Conference (DAC) 1994, pp. 56–62. assume that zero-delay input inverters are available on all gates, which is a violation of true speed-independence but is fairly safe in practice. Other examples of using this assumption also exist.{{cite journal | url=http://www.sciencedirect.com/science/article/pii/S0167926096000107 | doi=10.1016/S0167-9260(96)00010-7 | title=Modelling, analysis and synthesis of asynchronous control circuits using Petri nets | journal=Integration | date=December 1996 | volume=21 | issue=3 | pages=143–170 | last1=Yakovlev | first1=A. V. | last2=Koelmans | first2=A. M. | last3=Semenov | first3=A. | last4=Kinniment | first4=D. J. }}

Other technologies suitable for realizing asynchronous primitives including C-element, are: carbon nanotubes,{{Citation needed|date=December 2019|reason=removed citation to predatory publisher content}} single-electron tunneling devices,S. Safiruddin, S. D. Cotofana, [https://www.researchgate.net/profile/Sorin_Cotofana/publication/224326348_Building_Blocks_for_Delay-Insensitive_Circuits_using_Single_Electron_Tunneling_Devices/links/0c9605230deb723cac000000.pdf "Building blocks for delay-insensitive circuits using single electron tunneling devices"], IEEE Conference on Nanotechnology 2007, pp. 704–708. quantum dots,V. I. Varshavsky, [https://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=494973 "Logic design and quantum challenge"], Int. Workshop on Physics and Computer Modeling of Devices Based on Low-Dimensional Structures 1995, pp. 134–146. and molecular nanotechnology.A. J. Martin, P. Prakash, [http://www.async.caltech.edu/Pubs/PDF/2008_nano.pdf "Asynchronous nano-electronics: Preliminary investigation"] {{Webarchive|url=https://web.archive.org/web/20160304122447/http://www.async.caltech.edu/Pubs/PDF/2008_nano.pdf |date=2016-03-04 }}, IEEE Int. Symposium on Asynchronous Circuits and Systems (ASYNC) 2008, pp. 58–68.

The definition of C-element can be generalized for multiple-valued logic,[https://www.proquest.com/docview/303676273?pq-origsite=gscholar&fromopenview=true J. M. Johnson, Theory and Application of Self-Timed Integrated Systems Using Ternary Logic Elements. PhD thesis. University of California, Santa Barbara. 1989.][https://glim-re.repo.nii.ac.jp/record/3834/files/thesis_O79.pdf H. Sato, Completeness on Multiple-Valued Logical Functions Realized by Asynchronous Sequential Circuits. PhD thesis, Gakushuin University, 1996.] or even for continuous signals:

:$\backslash text\; \{\; if\; \}\; x\_1=x\_2=...=x\_m,\; \backslash text\; \{\; then\; \}\; y\_n=\backslash text\{any\}(x\_1,x\_2,...,x\_m),\; \backslash text\; \{\; else\; \}\; y\_n=y\_\{n-1\}.$

For example, the truth table for a balanced ternary C-element with two inputs is

Since the majority gate is a particular case of threshold gate, any of known realizations of threshold gateV. Beiu, J. M. Quintana, M. J. Avedillo, [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.11.2109&rep=rep1&type=pdf "VLSI implementations of threshold logic – A comprehensive survey"], IEEE Transactions on Neural Networks, vol. 14, no. 5, pp. 1217–1243, 2003. can in principle be used for building a C-element. In the multiple-valued case, however, connecting the output of majority gate to one or several inputs may have no desirable effect. For example, using the ternary majority function defined asV. Varshavsky, B. Ovsievich, [http://www.ee.bgu.ac.il/~kushnero/asynchronous/Varshavsky%20and%20Co/Networks%20Composed%20of%20Ternary%20Majority%20Elements.pdf "Networks composed of ternary majority elements"], IEEE Transactions on Electronic Computers, vol. EC-14, no. 5, pp. 730–733, 1965.

:$y\; =\; \backslash begin\{cases\}$

+1 & \text{if}\ x_1+x_2+x_3 \geqslant +1,\\

0 & \text{if}\ x_1+x_2+x_3 = 0,\\

-1 & \text{if}\ x_1+x_2+x_3 \leqslant -1

\end{cases}

does not lead to the ternary C-element specified by the truth table, if the sum $x\_1\; +\; x\_2\; +\; x\_3$ is not split into pairs. However, even without such a splitting two ternary majority functions are suitable for building a ternary inclusive OR gate.

{{Reflist|30em}}

• [https://workcraft.org/tutorial/design/c_element/start Workcraft tool: Synthesis and verification of C-element]

Category:Logic gates

Category:Digital electronics