Catapult C

In 2004, Mentor Graphics formally announced its Catapult C high level synthesis product offering hierarchical design support for synthesizing pipelined, multi-block subsystems from untimed ANSI C/C++ descriptions. Catapult C's main functionality was generating RTL (VHDL and Verilog) targeted to ASICs and FPGAs. Users specified constraints for timing and area, and provided a clock period and destination technology. Mentor also announced a Catapult C Library Builder for ASIC Designers to collect detailed characterization data.EETimes: [https://www.eetimes.com/high-level-synthesis-rollouts-enable-esl/ High-level synthesis rollouts enable ESL]

In 2005, Mentor announced extensions to Catapult C to automatically create SystemC transaction-level models and wrappers, for simulation of the design in verification environments supporting SystemC. Mentor also introduced interface synthesis to map the data transfer implied by passing of C++ function arguments to hardware interfaces such as wires, registers, handshakes registers, memories, buses or more complex user-defined interfaces.SOCCentral [http://www.soccentral.com/results.asp?EntryID=13121 Mentor Graphics Extends Catapult C Synthesis Product] {{Webarchive|url=https://web.archive.org/web/20060205101637/http://www.soccentral.com/results.asp?EntryID=13121 |date=2006-02-05 }}

In 2006, Mentor announced Catapult SL (System Level) for automatically creating signal processing subsystems. Catapult SL could coordinate the partitioning of sequential C operations into multiple blocks within the subsystem, including partitioning into multiple clock domains. Catapult SL automatically inserts appropriate inter-block channels and memory buffers to assemble the sub-system.SOCCentral [http://www.soccentral.com/results.asp?EntryID=19325 Mentor Introduces High-Level Synthesis to Create High-Performance Subsystems from Pure ANSI C++] {{Webarchive|url=https://archive.today/20120913221148/http://www.soccentral.com/results.asp?EntryID=19325 |date=2012-09-13 }}.

In January 2009, Mentor announced an integration between Catapult C and its Vista SystemC design and simulation environment to automatically generate transaction-level models (TLM). In this process, the untimed ANSI C++ input to Catapult is encapsulated in a TLM wrapper; timing information is extracted from the synthesis results and back-annotated in the resulting model. The flow is compatible with the TLM-2.0 standard from the Open SystemC Initiative (OSCI).EETimes [http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=212901482 Mentor TLM 2.0 design flow]

In June 2009, Mentor announced that it enhanced Catapult C with the ability to synthesize control logic, create power-optimized RTL netlists, with automatic multi-level clock gating, and an automated verification flow to enable a debug of the RTL against the original C++ input.SCDsource [http://scdsource.com/article.php?id=349 Mentor Catapult C synthesizes control and power management] {{webarchive|url=https://web.archive.org/web/20111009041028/http://scdsource.com/article.php?id=349 |date=2011-10-09 }}

In January 2010, Mentor announced the ability for Catapult C to take direct SystemC input, including both cycle-based and transaction level (TLM) support.Chip Design [http://chipdesignmag.com/display.php?articleId=3882 Bridging ESL and High-Level Synthesis]

In May 2011, Mentor announced that Catapult C supported TLM synthesis. Abstract TLM models are converted to pin-accurate, protocol-specific, SystemC models, and from there, synthesized to RTL code. Existing synthesizable descriptions can be converted to TLMs.EETimes [http://www.eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4216455/Mentor-s-TLM-Synthesis-links-virtual-prototyping-and-hardware-implementation Mentor’s TLM Synthesis links virtual prototyping and hardware implementation]

In August 2011, Catapult C was acquired by Calypto Design Systems.EETimes [http://www.eetimes.com/electronics-news/4219348/Calypto-acquires-Mentor-s-Catapult-C Calypto acquires Mentor's Catapult C]

In September 2015, Mentor Graphics acquired Calypto Design Systems,PR Newswire [https://www.prnewswire.com/news-releases/mentor-graphics-acquires-calypto-design-systems-300144394.html Mentor Graphics Acquires Calypto Design Systems] thus reacquiring Catapult C.

CatapultC synthesizes ANSI C/C++ without proprietary extensions. The C/C++ language support includes pointers, classes, templates, template specialization and operator overloading, which facilitate design reuse methodology over RTL code.University of Oulu [http://www.ee.oulu.fi/~cavallar/arch_course/papers/12_pres_myllyla.pdf Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA Wireless System Using C Synthesis]

Catapult C supports both algorithmic and control logic synthesis.SCDsource [http://scdsource.com/article.php?id=349 Mentor Catapult C synthesizes control and power management] {{webarchive|url=https://web.archive.org/web/20111009041028/http://scdsource.com/article.php?id=349 |date=2011-10-09 }}

Designers do iterations with CatC to pick their preferred micro architecture for specified performance and area constraints.ICASSP [http://www.icassp09.com/Papers/ViewPapers.asp?PaperNum=3199 Architectural Design and Implementation of the Increasing Radius – List Sphere Detector Algorithm] Catapult has a graphic user interface with a visual view of the hardware circuit it is scheduling, as well as the clock reference between the C code and the Verilog RTL code. Catapult C has 3 types of simulation using the original C/C++ testbench: Cycle-based, RTL-based, and Gate-Level based.Deepchip [http://www.deepchip.com/items/0477-03.html C/C++ chip design using high-level synthesis]

Catapult C supports SystemC model generation intended for virtual platforms, and a SystemC test environment to verify the generated RTL against the original C++ using the original C++ testbench.

Catapult C supports the synthesis of Transaction Level Models (TLM), including standard off-the-shelf bus interfaces and custom protocols.EETimes [http://www.eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4216455/Mentor-s-TLM-Synthesis-links-virtual-prototyping-and-hardware-implementation Mentor’s TLM Synthesis links virtual prototyping and hardware implementation]

• Stratus HLS from Cadence Design Systems
• Vivado HLS from Xilinx (formerly, AutoPilot from [http://www.eetimes.com/author.asp?section_id=36&doc_id=1284904 AutoESL])
• Intel HLS from Intel (formerly a++ from Altera)
• BlueSpec Compiler from [https://web.archive.org/web/20110317051752/http://www.bluespec.com/products/index.htm BlueSpec]
• Impulse C CoDeveloper from [http://www.impulseaccelerated.com/ Impulse Accelerated Technologies]
• Synphony C Compiler from Synopsys
• LegUp from [http://legup.eecg.utoronto.ca University of Toronto] {{Webarchive|url=https://web.archive.org/web/20200724081231/http://legup.eecg.utoronto.ca/ |date=2020-07-24 }}
• CyberWorkBench from NEC [http://www.edatechforce.com/our-clients/nec/cyberworkbench/]
• C-to-Verilog from [http://www.c-to-verilog.com C-to-Verilog.com]
• eXCite from [http://www.yxi.com Y Explorations] {{Webarchive|url=https://web.archive.org/web/20190917062628/http://www.yxi.com/ |date=2019-09-17 }}
• [http://parallel.cc ParC] C++ extended for parallel processing and hardware description
• HDL Coder from MathWorks
• PandA-Bambu HLS from Politecnico di Milano [https://panda.dei.polimi.it]

{{reflist|35em}}

• [http://calypto.com/en/products/catapult/overview/ Calypto Design Systems Catapult C Synthesis Product Page]
• [http://www.mentor.com/products/esl/high_level_synthesis/catapult_synthesis/ Mentor Graphics Catapult C Synthesis Product Page]
• [https://web.archive.org/web/20081121013040/http://communities.mentor.com/esl ESL and High-Level Synthesis Communities]
• [https://web.archive.org/web/20110603231314/http://www-rocq.inria.fr/~trifunov/ddecs06.pdf Transforming an ANSI C code with OpenMP directives into a SystemC description]
• [http://portal.acm.org/citation.cfm?id=1509635 Automated synthesis and verification of embedded systems: wishful thinking or reality?]

Category:Electronic design automation software