Chronologic Simulation

In the late 1980s and early 1990s integrated circuits were being designed and verified in Verilog HDL simulators.{{Cite web |title=A brief history of logic simulation |url=https://semiengineering.com/knowledge_centers/eda-design/verification/logic-simulation/a-brief-history-of-logic-simulation/ |access-date=2025-05-20 |website=Semiconductor Engineering |language=en-US}} These simulators were focused on gate level speed and were implemented as language interpreters. Verilog HDL{{Cite journal |last1=Flake |first1=Peter |last2=Moorby |first2=Phil |last3=Golson |first3=Steve |last4=Salz |first4=Arturo |last5=Davidmann |first5=Simon |date=2020-06-12 |title=Verilog HDL and its ancestors and descendants |url=https://dl.acm.org/doi/10.1145/3386337 |journal=Proc. ACM Program. Lang. |volume=4 |issue=HOPL |pages=87:1–87:90 |doi=10.1145/3386337|doi-access=free }} was proprietary and owned by Cadence Design Systems after their acquisition in1989 of Gateway Design Automation, the developers of Verilog.

There was competition to Verilog from the US DoD VHDL language that became an IEEE standard and in 1991 Cadence made the proprietary Verilog HDL public and created Open Verilog International (OVI) (later renamed Accellera) to standardize it.{{Cite web |title=Open Verilog International |url=https://semiengineering.com/entities/open-verilog-international/ |access-date=2025-05-20 |website=Semiconductor Engineering |language=en-US}}{{Cite web |last=Raval |first=Vrit |date=2019-08-24 |title=BRIEF HISTORY OF VERILOG ! |url=https://medium.com/verilog-novice-to-wizard/brief-history-of-verilog-eb836b823d15 |access-date=2025-05-20 |website=VERILOG NOVICE TO WIZARD |language=en}}

The founders of Chronologic{{Cite web |title=Chronologic Simulation |url=https://semiengineering.com/entities/chronologic-simulation/ |access-date=2025-05-20 |website=Semiconductor Engineering |language=en-US}} saw the opening up of Verilog as an opportunity to adopt software compiler techniques and create a fast compiled code Verilog simulator.{{Cite web |last=Sanguinetti |first=John |date=1993-09-11 |title=Simulation speed and logic design |url=https://www.computerhistory.org/collections/catalog/102624716 |website=computerhistory.org}}

• John Sanguinetti, CEO and founder
• Peter Eichenberger, CTO and founder
• Michael McNamara, VP Engineering
• Martin Harding, VP Sales{{Cite journal |date=2006 |title=SystemVerilog for Design |url=https://link.springer.com/book/10.1007/0-387-36495-1 |journal=SpringerLink |language=en |doi=10.1007/0-387-36495-1 |isbn=978-0-387-33399-1}}
• Simon Davidmann, VP Europe

The development of the Verilog Compiled Simulator (VCS) started in 1991 with early development by Sanguinetti,{{Cite web |title=John Sanguinetti - A Profile |url=http://www.aycinena.com/index2/index3/archive/john%20sanguinetti.html |access-date=2025-05-20 |website=www.aycinena.com}}{{Cite web |last=Sanguinetti |first=John |date=2009-02-28 |title=Oral History of John Sanguinetti |url=https://archive.computerhistory.org/resources/access/text/2015/06/102702042-05-01-acc.pdf |website=archive.computerhistory.org}} Eichenberger, and McNamara and by 1993 the first version was released, Harding and Davidmann started up the sales channel, and VCS was in use with commercial users and in education and research.{{Cite book |last=Olukotun |first=Kunle |title=Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95 |date=1994-07-04 |chapter=A General Method for Compiling Event-Driven Simulations |chapter-url=https://dl.acm.org/doi/pdf/10.1145/217474.217522 |pages=151–156 |doi=10.1145/217474.217522 |isbn=0-89791-725-1 }}{{Cite web |last=Palnitkar |first=Samir |date=1995-03-27 |title=Cycle simulation techniques |url=http://archive.sigda.org/programs/cadathlon/refs/p5-verification.pdf |website=archive.sigda.org}}{{Cite book |last1=Wang |first1=Tsu-Hua |last2=Tan |first2=Chong Guan |chapter=Practical code coverage for Verilog |date=March 1995 |title=Proceedings. 1995 IEEE International Verilog HDL Conference |chapter-url=https://ieeexplore.ieee.org/document/512503 |pages=99–104 |doi=10.1109/IVC.1995.512503|isbn=0-8186-7082-7 }}{{Cite web |title=Using VCS |url=https://www.cs.utexas.edu/~fussell/courses/cs352h/handouts/verilog/vcs_tut.html |access-date=2025-05-20 |website=www.cs.utexas.edu}} VCS initially parsed the Verilog source and using software compiler techniques created C code which is then subsequently compiled into executable binaries to run on the native host computer.{{Cite web |last=Murphy |first=Sean |date=2009-05-20 |title=Interview with John Sanguinetti |url=https://www.skmurphy.com/blog/2009/05/19/interview-with-john-sanguinetti/ |access-date=2025-05-20 |website=SKMurphy, Inc. |language=en-US}} The performance of existing Verilog simulators was excellent at the gate level but lacked needed speed at the RTL level. Chronologic's VCS focused on RTL speed and by using cycle based and complier optimization techniques was often reported as being 10-40 times faster than other commercial products.{{Cite news |last=Wharton |first=David |date=1994-06-01 |title=Benchmarks Test a Few Simulators |work=Electronic Engineering Times (EE Times) |pages=50–52, 92}}{{Cite journal |last=Thomas |first=Don |date=1994-03-07 |title=Benchmark descriptions for comparing the performance of Verilog and VHDL simulators |journal=Proceedings of the 1994 International Verilog HDL Conference |volume=1994 |pages=14–16}}{{Cite web |last=EETimes |date=1996-10-07 |title=Chronologic VCS 3.1 Increases Accurate Gate-Level Performance |url=https://www.eetimes.com/chronologic-vcs-3-1-increases-accurate-gate-level-performance/ |access-date=2025-05-20 |website=EE Times}}

Chronologic Simulation was acquired in 1994 for $26.5 million by Viewlogic Systems, Inc. though there were complications that resulted in lawsuits that were ultimately resolved in 1995.{{Cite web |title=Chronologic Simulation, Inc. v. Sanguinetti, 892 F. Supp. 318 (D. Mass. 1995) |url=https://law.justia.com/cases/federal/district-courts/FSupp/892/318/2295715/ |access-date=2025-05-20 |website=Justia Law |language=en}}{{Cite web |title=Viewlogic Systems, Inc. |url=https://semiengineering.com/entities/viewlogic-systems-inc/ |access-date=2025-05-20 |website=Semiconductor Engineering |language=en-US}}{{Cite web |title=Viewlogic settles with Chronologic - ProQuest |url=https://www.proquest.com/docview/208126322 |access-date=2025-05-20 |website=www.proquest.com | id={{ProQuest|208126322}} |language=en}} In 1997 Synopsys, Inc., acquired Viewlogic for $497 million.{{Cite web |last=Writer |first=CBR Staff |date=1997-10-16 |title=SYNOPSYS ACQUIRES VIEWLOGIC FOR $500M |url=https://www.techmonitor.ai/technology/synopsys_acquires_viewlogic_for_500m |access-date=2025-05-20 |website=Tech Monitor |language=en-US}}{{Cite web |last=EETimes |date=1997-12-08 |title=Shareholders Approve Synopsys/Viewlogic Merger |url=https://www.eetimes.com/shareholders-approve-synopsys-viewlogic-merger/ |access-date=2025-05-20 |website=EE Times}}

VCS is still widely used and has been kept up to date with the evolution in the Verilog language, including features from Superlog that became part of SystemVerilog around 2005. VCS is still a part of Synopsys verification solutions.{{Cite web |date=2024-03-01 |title=VCS Datasheet |url=https://www.synopsys.com/content/dam/synopsys/gated-assets/verification/vcs-ds.pdf |website=www.synopsys.com}}{{Cite web |title=VCS: Functional Verification Solution {{!}} Synopsys |url=https://www.synopsys.com/verification/simulation/vcs.html |access-date=2025-05-20 |website=www.synopsys.com |language=en}}

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