Circuit design language

{{Short description|Type of netlist}}

{{More citations needed|date=August 2023}}

{{Use American English|date = April 2019}}

A circuit design language (CDL) is a kind of netlist, a description of an electronic circuit.{{cite book|last=Doman|first=David|title=Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon|url=https://books.google.com/books?id=XmIEset3uGYC&pg=PA256|year=2012|publisher=John Wiley & Sons|isbn=978-1-118-24304-6|page=256}} It is usually automatically generated from a circuit schematic. It is used for electronic circuit simulation and layout versus schematic (LVS) checks. It is similar to SPICE netlists, but with some extensions.

Several vendors such as Cadence Design Systems, Mentor Graphics, and Synopsys support CDL netlists, although their solutions may be proprietary and not readable by competing systems.