Comparison of instruction set architectures
{{Short description|none}}
An instruction set architecture (ISA) is an abstract model of a computer, also referred to as computer architecture. A realization of an ISA is called an implementation. An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost (among other things); because the ISA serves as the interface between software and hardware. Software that has been written for an ISA can run on different implementations of the same ISA. This has enabled binary compatibility between different generations of computers to be easily achieved, and the development of computer families. Both of these developments have helped to lower the cost of computers and to increase their applicability. For these reasons, the ISA is one of the most important abstractions in computing today.
An ISA defines everything a machine language programmer needs to know in order to program a computer. What an ISA defines differs between ISAs; in general, ISAs define the supported data types, what state there is (such as the main memory and registers) and their semantics (such as the memory consistency and addressing modes), the instruction set (the set of machine instructions that comprises a computer's machine language), and the input/output model.
Data representation
In the early decades of computing, there were computers that used binary, decimal{{cite web|last=da Cruz|first=Frank|title=The IBM Naval Ordnance Research Calculator|publisher=Columbia University Computing History|date=October 18, 2004|url=https://www.columbia.edu/cu/computinghistory/norc.html|access-date=May 8, 2024}} and even ternary.{{cite web|url=http://www.computer-museum.ru/english/galglory_en/Brusentsov.htm|title=Russian Virtual Computer Museum _ Hall of Fame _ Nikolay Petrovich Brusentsov}}{{cite book|last1=Trogemann|first1=Georg|last2=Nitussov|first2=Alexander Y.|last3=Ernst|first3=Wolfgang|isbn=978-3-528-05757-2|pages=19, 55, 57, 91, 104–107|publisher=Vieweg+Teubner Verlag|title=Computing in Russia: the history of computer devices and information technology revealed|year=2001}}. Contemporary computers are almost exclusively binary.
Characters are encoded as strings of bits or digits, using a wide variety of character sets; even within a single manufacturer there were character set differences.
Integers are encoded with a variety of representations, including Sign-magnitude, Ones' complement, Two's complement, Offset binary, Nines' complement and Ten's complement.
Similarly, floating point numbers are encoded with a variety of representations for the sign, exponent and mantissa. In contemporary machines IBM hexadecimal floating-point and IEEE 754 floating point have largely supplanted older formats.
Addresses are typically unsigned integers generated from a combination of fields in an instruction, data from registers and data from storage; the details vary depending on the architecture.
= Bits =
Computer architectures are often described as n-bit architectures. In the first {{frac|3|4}} of the 20th century, n is often 12, 18, 24, 30, 36, 48 or 60. In the last {{frac|1|3}} of the 20th century, n is often 8, 16, or 32, and in the 21st century, n is often 16, 32 or 64, but other sizes have been used (including 6, 39, 128). This is actually a simplification as computer architecture often has a few more or less "natural" data sizes in the instruction set, but the hardware implementation of these may be very different. Many instruction set architectures have instructions that, on some implementations of that instruction set architecture, operate on half and/or twice the size of the processor's major internal datapaths. Examples of this are the Z80, MC68000, and the IBM System/360. On these types of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The IBM System/360 instruction set architecture is 32-bit, but several models of the System/360 series, such as the IBM System/360 Model 30, have smaller internal data paths, while others, such as the 360/195, have larger internal data paths. The external databus width is not used to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses; the NS32764 had a 64-bit bus, and used 32-bit register. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors.
= Digits =
In the first {{frac|3|4}} of the 20th century, word oriented decimal computers typically had 10 digit{{cite book
| title = 650 magnetic drum data processing machine
| id = 22-6060-2
| date = June 1955
| url = http://bitsavers.org/pdf/ibm/650/22-6060-2_650_OperMan.pdf
| publisher = IBM
| access-date = May 8, 2024
}}
| title = IBM 7070-7074 Principles of Operation
| id = GA22-7003-6
| year = 1962
| url = http://bitsavers.org/pdf/ibm/7070/GA22-7003-6_7070-7074prcOps.pdf
| series = Systems Reference Library
| publisher = IBM
| access-date = May 8, 2024
}}
| title = UNIVAC® Solid-state 80 Computer
| id = U1742.1r3
| year = 1959
| url = http://bitsavers.org/pdf/univac/uss/U1742.1r3_UNIVAC_Solid-State_80_General_Description_1959.pdf
| publisher = Sperry Rand Corporation
| access-date = May 8, 2024
}}
words with a separate sign,{{efn|Normally the sign could only be plus or minus, but on the IBM 7070/72/74 there was a 3-state sign.}} using all ten digits in integers and using two digits for exponents{{cite book
| title = IBM 650 MDDPM Additional Features - Indexing Accumulators - Floating-Decimal Arithmetic - Advanced Write-Up
| id = 22-6258-0
| year = 1955
| url = http://bitsavers.org/pdf/ibm/650/22-6258-0_FeaturesIdxAccum.pdf
| publisher = IBM
| access-date = May 8, 2024
}}
= Endianness =
An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little-endian processors order bytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big-endian architectures instead arrange bytes with the most significant byte at the lowest-numbered address. The x86 architecture as well as several 8-bit architectures are little-endian. Most RISC architectures (SPARC, Power, PowerPC, MIPS) were originally big-endian (ARM was little-endian), but many (including ARM) are now configurable as either.
Endianness only applies to processors that allow individual addressing of units of data (such as bytes) that are smaller than some of the data formats.
Instruction formats
= Opcodes =
In some architectures, an instruction has a single opcode. In others, some instructions have an opcode and one or more modifiers. E.g., on the IBM System/370, byte 0 is the opcode but when byte 0 is a {{base|B2|16}} then byte 1 selects a specific instruction, e.g., {{base|B205|16}} is store clock (STCK).
= Operands =
== Addressing modes ==
{{main|addressing mode}}
Architectures typically allow instructions to include some combination of operand addressing modes:
;Direct
:The instruction specifies a complete address
;Immediate
:The instruction specifies a value rather than an address
;Indexed
:The instruction specifies a register to use as an index. In some architecture the index is scaled by the operand length.
;Indirect
:The instruction specifies the location of a pointer word that describes the operand, possibly involving multiple levels of indexing and indirection
;Truncated
;Base-displacement
:The instruction specifies a displacement from an address in a register
;autoincrement/autodecrement
:A register used for indexing, or a pointer word used by indirect addressing, is incremented or decremented by 1, an operand size or an explicit delta
== Number of operands ==
{{Main| instruction set#Number of operands}}
The number of operands is one of the factors that may give an indication about the performance of the instruction set.
A three-operand architecture (2-in, 1-out) will allow
A := B + C
to be computed in one instruction
ADD B, C, A
A two-operand architecture (1-in, 1-in-and-out) will allow
A := A + B
to be computed in one instruction
ADD B, A
but requires that
A := B + C
be done in two instructions
MOVE B, A
ADD C, A
= Encoding length =
Instruction sets
{{confusing section|reason=Open and Royalty free are not defined and most entries are unsourced|date=October 2021}}
The table below compares basic information about instruction set architectures.
Notes:
- Usually the number of registers is a power of two, e.g. 8, 16, 32. In some cases a hardwired-to-zero pseudo-register is included, as "part" of register files of architectures, mostly to simplify indexing modes. The column "Registers" only counts the integer "registers" usable by general instructions at any moment. Architectures always include special-purpose registers such as the program counter (PC). Those are not counted unless mentioned. Note that some architectures, such as SPARC, have register windows; for those architectures, the count indicates how many registers are available within a register window. Also, non-architected registers for register renaming are not counted.
- In the "Type" column, "Register–Register" is a synonym for a common type of architecture, "load–store", meaning that no instruction can directly access memory except some special ones, i.e. load to or store from register(s), with the possible exceptions of memory locking instructions for atomic operations.
- In the "Endianness" column, "Bi" means that the endianness is configurable.
{{sticky header}}
{{sort-under}}
{{mw-datatable}}
| class="wikitable sticky-header sortable sort-under mw-datatable" border="1" style="font-size:85%;"
! {{verth|Architecture}} ! Bits ! Version ! {{verth|Introduced}} ! Max # ! Type ! Design ! Registers ! Instruction encoding ! Branch evaluation ! {{verth|Endianness}} ! Extensions ! Open ! Royalty |
| 6502
| 8 | | 1975 | 1 | CISC | 3 | Variable | Condition register | Little | | | |
| 6800
| 8 | | 1974 | 1 | Register–Memory | CISC | 3 | Variable | Condition register | Big | | | |
| 6809
| 8 | | 1978 | 1 | Register–Memory | CISC | 5 | Variable | Condition register | Big | | | |
| 680x0
| 32 | | 1979 | 2 | Register–Memory | CISC | 8 data and 8 address | Variable | Condition register | Big | | | |
| 8080
| 8 | | 1974 | 2 | Register–Memory | CISC | 7 | Variable | Condition register | Little | | | |
| 8051
| 32 | | 1977? | 1 | CISC | {{ubl|32 in 4-bit|16 in 8-bit|8 in 16-bit|4 in 32-bit}} | Variable | Compare and branch | Little | | | |
| x86
| 16, 32, 64 | v4 (x86-64) | 1978 | 2 (integer) | Register–Memory | CISC | {{ubl|8 (+ 4 or 6 segment reg.) | Variable | Condition code | Little | x87, IA-32, MMX, 3DNow!, SSE, | {{No}} | {{No}} |
| Alpha
| 64 | | 1992 | 3 | Register–Register | RISC | 32 (including "zero") | Fixed | Condition register | Bi | {{tooltip|2=Motion Video Instructions|MVI}}, {{tooltip|2=Byte-Word Extensions|BWX}}, {{tooltip|2=Floating-point Extensions|FIX}}, {{tooltip|2=Count Extensions|CIX}} | {{No}} | |
| ARC
| 16/32/64 (32→64) | 1996 | 3 | Register–Register | RISC | 16 or 32 including SP | Variable | Compare and branch | Bi | APEX User-defined instructions | | |
| ARM/A32
| 32 | ARMv1–v9 | 1983 | 3 | Register–Register | RISC | {{ubl|15}} | Fixed | Condition code | Bi | NEON, Jazelle, {{tooltip|2=Vector Floating Point|VFP}}, | | {{No}} |
| Thumb/T32
| 32 | ARMv4T-ARMv8 | 1994 | 3 | Register–Register | RISC | {{ubl|7 with 16-bit Thumb instructions|15 with 32-bit Thumb-2 instructions}} | Thumb: Fixed | Condition code | Bi | NEON, Jazelle, {{tooltip|2=Vector Floating Point|VFP}}, | | {{No}} |
| Arm64/A64
| 64 | v8.9-A/v9.4-A, | 2011 | 3 | Register–Register | RISC | 32 (including the stack pointer/"zero" register) | Fixed | Condition code | Bi | SVE and SVE2 | | {{No}} |
| AVR
| 8 | | 1997 | 2 | Register–Register | RISC | 32 | Variable (mostly 16-bit, four instructions are 32-bit) | Condition register, | Little | | | |
| AVR32
| 32 | Rev 2 | 2006 | 2–3 | | RISC | 15 | Variable | | Big | | |
| Blackfin
| 32 | | 2000 | Register–Register | RISC | 2 accumulators 8 data registers 8 pointer registers 4 index registers 4 buffer registers | Variable (16- or 32-bit) | Condition code | Little | | | |
| CDC Upper 3000 series
| 48 | | 1963 | 3 | Register–Memory | CISC | 48-bit A reg., 48-bit Q reg., 6 15-bit B registers, miscellaneous | Variable | Multiple types of jump and skip | Big | | | |
| CDC 6000 Central Processor (CP) | 60 | | 1964 | 3 | Register–Register | {{n/a|N/A}}{{efn|partly RISC: load/store architecture and simple addressing modes, partly CISC: three instruction lengths and no single instruction timing}} | 24 (8 18-bit address reg., | Variable | Compare and branch | {{n/a|N/A}}{{efn|Since memory is an array of 60-bit words with no means to access sub-units, big endian vs. little endian makes no sense. The optional CMU unit uses big-endian semantics.}} | Compare/Move Unit | {{No}} | {{No}} |
| CDC 6000 Peripheral Processor (PP) | 12 | | 1964 | 1 or 2 | Register–Memory | CISC | 1 18-bit A register, locations 1–63 serve as index registers for some instructions | Variable | Test A register, test channel | {{n/a|N/A}}{{efn|Since memory is an array of 12-bit words with no means to access sub-units, big endian vs. little endian makes no sense.}} | additional Peripheral Processing Units | {{No}} | {{No}} |
| Crusoe (native VLIW) | | 2000 | 1 | Register–Register | VLIW | {{ubl|1 in native push stack mode|6 in x86 emulation + | Variable | Little | | | |
| Elbrus 2000 (native VLIW) | 64 | v6 | 2007 | 1 | VLIW | 8–64 | 64 | Condition code | Little | Just-in-time dynamic translation: x87, IA-32, MMX, SSE, | {{No}} | {{No}} |
| DLX
| 32 | {{dunno}} | 1990 | 3 | Register–Register | RISC | 32 | Fixed | Condition register | Big | {{dunno}} | {{Yes}} | {{dunno}} |
| eSi-RISC
| 16/32 | | 2009 | 3 | Register–Register | RISC | 8–72 | Variable (16- or 32-bit) | Compare and branch | Bi | User-defined instructions | {{No}} | {{No}} |
| iAPX 432{{Cite book|last=Intel Corporation|title=Introduction to the iAPX 432 Architecture|year=1981|pages=iii|url=http://bitsavers.org/components/intel/iAPX_432/171821-001_Introduction_to_the_iAPX_432_Architecture_Aug81.pdf}}
| 32 | | 1981 | 3 | CISC | 0 | Variable (6 to 321 bits) | | | | {{No}} | {{No}} |
| Itanium (IA-64) | 64 | | 2001 | | Register–Register | EPIC | 128 | Fixed | Condition register | Bi | Intel Virtualization Technology | {{No}} | {{No}} |
| LoongArch
| 32, 64 | | 2021 | 4 | Register–Register | RISC | 32 (including "zero") | Fixed (32-bit) | | Little | | {{No}} | {{No}} |
| M32R
| 32 | | 1997 |3 | Register–Register | RISC | 16 | Variable |Condition register | Bi | | | |
| m88k
| 32 | | 1988 | 3 | Register–Register | RISC | 32 | Fixed | Compare and branch | Big | | | |
| Mico32
| 32 | {{dunno}} | 2006 | 3 | Register–Register | RISC | 32 | Fixed | Compare and branch | Big | User-defined instructions | {{Yes}} | {{Yes}} |
| MIPS
| 64 | 6 | 1981 | 1–3 | Register–Register | RISC | 4–32 (including "zero") | Fixed | Condition register | Bi | {{No}} | {{No}} |
| MMIX
| 64 | {{dunno}} | 1999 | 3 | Register–Register | RISC | 256 | Fixed | Condition register | Big | {{dunno}} | {{Yes}} | {{Yes}} |
| Nios II
| 32 | {{dunno}} | 2000 | 3 | Register–Register | RISC | 32 | Fixed (32-bit) | Condition register | Little | Soft processor that can be instantiated on an Altera FPGA device | {{No}} | {{partial|On Altera/Intel FPGA only}} |
| Nova
| 16 | | 1969 | 2 | Register–Register | CISC | 4 | Fixed | Skip | None | | | |
| NS320xx
| 32 | | 1982 | 5 | Memory–Memory | CISC | 8 | Variable Huffman coded, up to 23 bytes long | Condition code | Little | BitBlt instructions | | |
| OpenRISC
| 32, 64 | 1.4 | 2000 | 3 | Register–Register | RISC | 16 or 32 | Fixed | Condition code | Bi | {{dunno}} | {{Yes}} | {{Yes}} |
| PA-RISC (HP/PA) | 64 | 2.0 | 1986 | 3 | Register–Register | RISC | 32 | Fixed | Compare and branch | Big → Bi | MAX | {{No}} | |
| PDP-5 {{Cite book|url=http://www.bitsavers.org/pdf/dec/pdp5/F-55_PDP5Handbook_Feb64.pdf|title=PDP-5 Handbook|date=February 1964|publisher=Digital Equipment Corporation}} PDP-8 {{Cite book|url=http://www.bitsavers.org/pdf/dec/pdp8/pdp8/F-85_PDP-8_Users_Handbook_May66.pdf|title=PDP-8 Users Handbook|date=May 1966|publisher=Digital Equipment Corporation}} | 12 | | 1963 | | Register–Memory | CISC | 1 accumulator 1 multiplier quotient register | Fixed | Condition register Test and branch | | EAE (Extended Arithmetic Element) | | |
| PDP-11
| 16 | | 1970 | 2 | Memory–Memory | CISC | 8 (includes program counter and stack pointer, though any register can act as stack pointer) | Variable | Condition code | Little | Extended Instruction Set, Floating Instruction Set, Floating Point Processor, Commercial Instruction Set | {{No}} | {{No}} |
| POWER, PowerPC, Power ISA
| 32/64 | 1990 | 3 (mostly). FMA, LD/ST-Update | Register–Register | RISC | 32 GPR, 8 4-bit Condition Fields, Link Register, Counter Register | Fixed | Condition code, Branch-Counter auto-decrement | Bi | AltiVec, APU, VSX, Cell, Floating-point, Matrix Multiply Assist | {{Yes}} | {{Yes}} |
| RISC-V
| 32, 64, 128 | 2010 | 3 | Register–Register | RISC | 32 (including "zero") | Variable |Compare and branch | Little | {{dunno}} | {{Yes}} | {{Yes}} |
| RX
| 64/32/16 | | 2000 | 3 | Memory–Memory | CISC | 4 integer + 4 address | Variable | Compare and branch | Little | | | {{No}} |
| S+core
| 16/32 | | 2005 | | | RISC | | | | Little | | | |
| SPARC
| 64 | 1985 | 3 | Register–Register | RISC | 32 (including "zero") | Fixed | Condition code | Big → Bi | VIS | {{Yes}} | {{Yes}} |
| SuperH (SH)
| 32 | {{dunno}} | 1994 | 2 | Register–Register | RISC | 16 | Fixed | Condition code | Bi | {{dunno}} | {{Yes}} | {{Yes}} |
| System/360 System/370 System/390 z/Architecture | 64 | | 1964 | 2 (most) | Register–Memory | CISC | 16 general | Variable | Condition code, compare and branch {{bracket|auto increment}}, Branch-Counter auto-decrement | Big | | {{No}} | {{No}} |
| TMS320 C6000 series
| 32 | | 1983 | 3 | Register-Register | VLIW | 32 on C67x | Fixed | Condition register | Bi | |{{No}} |{{No}} |
| Transputer
| 32 | | 1987 | 1 | MISC | 3 (as stack) | Fixed | Compare and branch | Little | | | |
| VAX
| 32 | | 1977 | 6 | Memory–Memory | CISC | 16 | Variable | Condition code, compare and branch | Little | | {{No}} | |
| Z80
| 8 | | 1976 | 2 | Register–Memory | CISC | 17 | Variable | Condition register | Little | | | |
See also
Notes
{{notelist}}