Control register

{{short description|Processor register which changes or controls the general behavior of a CPU}}

A control register is a processor register that changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.

History

{{expand section|dates for IBM, Intel and other vendors|date=May 2023}}

The early CPU lacked dedicated control registers, and relied on a limited set of internal signals and flags.{{Cite web |date=March 17, 2024 |title=lab4.pdf |url=https://www.it.uu.se/edu/course/homepage/mil/vt13/labcourse/lab4.pdf |url-status=live |archive-url=https://web.archive.org/web/20210117180151/https://www.it.uu.se/edu/course/homepage/mil/vt13/labcourse/lab4.pdf |archive-date=January 17, 2021 |access-date=March 16, 2024 |website=Uppsala University}} When IBM developed a paging version{{noteTag|IBM never shipped the 360/64 or 360/66, only the 360/67.}} of the System/360, they added 16 control registers{{sfn|M67prelim|pp=[http://bitsavers.org/pdf/ibm/360/model67/C20-1647-0_System_360_Model_67_Time_Sharing_System_Preliminary_Technical_Summary_1966.pdf#page=25 25-26]|loc=Control

Registers }}{{sfn|M67|p=[http://bitsavers.org/pdf/ibm/360/functional_characteristics/GA27-2719-2_360-67_funcChar.pdf#page=16 16]|loc=Table 4. Control Registers}} to the design for what became the 360/67. IBM did not provide control registers on other S/360 models, but made them a standard part{{sfn|S/370|pp=[http://bitsavers.org/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf#page=81 4-8-4-11 ]|loc=Control Registers}} of System/370, although with different register and bit assignments. As IBM added new features to the architecture, e.g., DAS, S/370-XA, S/370-ESA, ESA/390, they added additional fields to the control registers. With z/Architecture, IBM doubled the control register size to 64 bits.

Control registers in IBM 360/67

On the 360/67, CR0 and CR2 are used by address translation, CR 4-6 contain miscellaneous flags including interrupt masks and Extended Control Mode,{{sfn|M67|p=[http://bitsavers.org/pdf/ibm/360/functional_characteristics/GA27-2719-2_360-67_funcChar.pdf#page=16 16]|loc=Table 4. Control Registers}} and CR 8-14{{sfn|M67|pp=[http://bitsavers.org/pdf/ibm/360/functional_characteristics/GA27-2719-2_360-67_funcChar.pdf#page=31 31-35]|loc=Control Register Bit Assignments for Sensing}} contain the switch settings on the 2167 Configuration Unit.

= M67 CR0 =

Control Register 0 contains the address of the segment table for dynamic address translation.

= M67 CR2 =

Control register 2 is the Relocation exception address register.

= M67 CR4 =

CR4 is the extended mask register for channels 0-31.

Each bit is the 1/0 channel mask for the corresponding channel.

= M67 CR5 =

CR5 is reserved for the extended mask register for channels 32–63.

Each bit is the 1/0 channel mask for the corresponding channel.

= M67 CR6 =

CR6 contains two mode flags plus extensions to the PSW mask bits.

class="wikitable"

|+ CR6 Flags and Masks

! Field !! Bit !! Description

| 0

| Machine Check Mask Extension for Channel Controller o

| 1

| Machine Check Mask Extension for Channel Controller 1

2-3

| Reserved for channel controllers 2-3

4-7

| Unassigned

| 8

| Extended Control Mode

| 9

| Configuration Control Bit

10-23

| Unassigned

24-31

| External interrupt masking

| 24

| Timer

| 25

| Interrupt Key

| 26

| Malfunction Alert - CPU 1 (Ext. Sig. 2)

| 27

| Malfunction Alert - CPU 2 (Ext. Sig. 3)

| 28

| Reserved (Ext. Sig. 4)

| 29

| Reserved (Ext. Sig. 5)

| 30

| External Interrupt - CPU 1, 2 (Ext. Sig. 6)

| 31

| Reserved (Ext. Sig. 7)

= M67 CR8 =

Control Register 8 contains the assignments of Processor Storage units 1–4 to central processing units (CPUs) and channel controllers (CCs).

class="wikitable"

|+ Processor Storage unit 1-4 assignment

! Bit !! Description

| Processor Storage Unit 1 to CPU 1

| Processor Storage Unit 1 to CPU 2

2-3

| Reserved for CPU 3-4

| Processor Storage Unit 1 to CC 0

| Processor Storage Unit 1 to CC 1

6-7

| Reserved for CC 3-4

| Processor Storage Unit 2 to CPU 1

| Processor Storage Unit 2 to CPU 2

10-11

| Reserved for CPU 3-4

| Processor Storage Unit 2 to CC 0

| Processor Storage Unit 2 to CC 1

14-15

| Reserved for CC 3-4

| Processor Storage Unit 3 to CPU 1

| Processor Storage Unit 3 to CPU 2

18-19

| Reserved for CPU 3-4

| Processor Storage Unit 3 to CC 0

| Processor Storage Unit 3 to CC 1

22-23

| Reserved for CC 3-4

| Processor Storage Unit 4 to CPU 1

| Processor Storage Unit 4 to CPU 2

26-27

| Reserved for CPU 3-4

| Processor Storage Unit 4 to CC 0

| Processor Storage Unit 4 to CC 1

30-31

| Reserved for CC 3-4

= M67 CR9 =

Control Register 9 contains the assignments of Processor Storage units 5–8 to central processing units (CPUs) and channel controllers (CCs).

class="wikitable"

|+ Processor Storage unit 1-4 assignment

! Bit !! Description

| Processor Storage Unit 5 to CPU 1

| Processor Storage Unit 5 to CPU 2

2-3

| Reserved for CPU 3-4

| Processor Storage Unit 5 to CC 0

| Processor Storage Unit 5 to CC 1

6-7

| Reserved for CC 3-4

| Processor Storage Unit 6 to CPU 66

| Processor Storage Unit 6 to CPU 2

10-11

| Reserved for CPU 3-4

| Processor Storage Unit 6 to CC 0

| Processor Storage Unit 6 to CC 1

14-15

| Reserved for CC 3-4

| Processor Storage Unit 7 to CPU 1

| Processor Storage Unit 7 to CPU 2

18-19

| Reserved for CPU 3-4

| Processor Storage Unit 7 to CC 0

| Processor Storage Unit 7 to CC 1

22-23

| Reserved for CC 3-4

| Processor Storage Unit 8 to CPU 1

| Processor Storage Unit 8 to CPU 2

26-27

| Reserved for CPU 3-4

| Processor Storage Unit 8 to CC 0

| Processor Storage Unit 8 to CC 1

30-31

| Reserved for CC 3-4

= M67 CR10 =

Control Register 10 contains the Processor storage address assignment codes.

class="wikitable"

|+ Processor storage address bits 11-14 assignment codes

! Bit !! Starting Address Code for

0-3

| Processor Storage Unit 1

4-7

| Processor Storage Unit 2

8-11

| Processor Storage Unit 3

12-15

| Processor Storage Unit 4

16-19

| Processor Storage Unit 5

20-23

| Processor Storage Unit 6

24-27

| Processor Storage Unit 7

28-31

| Processor Storage Unit 8

= M67 CR11 =

Control Register 11 contains channel controller (CC) assignments.

class="wikitable"

|+ CR11 Channel Controller (CC) partitioning

! Bit !! Description

| CC 0 available on CPU 1

| CC 0 available on CPU 2

2-3

| Reserved for CPUs 3-4

| CC 1 available on CPU 1

| CC 1 available on CPU 2

6-7

| Reserved for CPUs 3-4

8-15

| Unassigned

| CPU 1 to only CC 0

| CPU 1 to only CC 1

18-19

| Reserved for CC 2-3

| CPU 2 to only CC 0

| CPU 2 to only CC 1

22-23

| Reserved for CC 2-3

24-31

| Unassigned

= M67 CR12 =

CR12 contains I/O Control Unit Partitioning.

class="wikitable"

|+ CR12 I/O Control Unit 1-16 Partitioning

! Bit !! I/O Control Unit !! Interface

| rowspan=2 | 1

| 1

| 2

| rowspan=2 | 2

| 1

| 2

| rowspan=2 | 3

| 1

| 2

| rowspan=2 | 4

| 1

| 2

| rowspan=2 | 5

| 1

| 2

| rowspan=2 | 6

| 1

| 2

| rowspan=2 | 7

| 1

| 2

| rowspan=2 | 8

| 1

| 2

| rowspan=2 | 9

| 1

| 2

| rowspan=2 | 10

| 1

| 2

| rowspan=2 | 11

| 1

| 2

| rowspan=2 | 12

| 1

| 2

| rowspan=2 | 13

| 1

| 2

| rowspan=2 | 14

| 1

| 2

| rowspan=2 | 15

| 1

| 2

| rowspan=2 | 16

| 1

| 2

= M67 CR13 =

CR13 contains I/O Control Unit Partitioning.

class="wikitable"

|+ CR13 I/O Control Unit 17-32 Partitioning

! Bit !! I/O Control Unit !! Interface

| rowspan=2 | 17

| 1

| 2

| rowspan=2 | 18

| 1

| 2

| rowspan=2 | 19

| 1

| 2

| rowspan=2 | 20

| 1

| 2

| rowspan=2 | 21

| 1

| 2

| rowspan=2 | 22

| 1

| 2

| rowspan=2 | 23

| 1

| 2

| rowspan=2 | 24

| 1

| 2

| rowspan=2 | 25

| 1

| 2

| rowspan=2 | 26

| 1

| 2

| rowspan=2 | 27

| 1

| 2

| rowspan=2 | 28

| 1

| 2

| rowspan=2 | 29

| 1

| 2

| rowspan=2 | 30

| 1

| 2

| rowspan=2 | 31

| 1

| 2

| rowspan=2 | 32

| 1

| 2

= M67 CR14 =

CR14 contains indicators.

class="wikitable"

|+ CR14 Indicators

! Bit !! Indicator

0-27

| Unassigned

| 2167 Power On

| Unassigned

| Direct Control, CPU 1

| Direct Control, CPU 2

26-27

| Unassigned

| Prefix, CPU 1

| Prefix, CPU 2

30-31

| Unassigned

Control registers in IBM S/390

The control registers of ESA/390{{sfn|S/390-ESA}} on the IBM S/390 are an evolutionary enhancement to the control registers on the earlier ESA/370,{{sfn|S/370-ESA}} S/370-XA{{sfn|S/370-XA}} and S/370{{sfn|S/370}} processors. For details on which fields are dependent on specific features, consult the Principles of Operation.{{sfn

| S/390-ESA

| pp = [http://publibz.boulder.ibm.com/epubs/pdf/dz9ar008.pdf#page=116 4-6-4-10]

| loc = Control Registers

}}

class="wikitable"

|+ ESA/390 control registers

! CR !! bits !! Field

id="ESA/390 CR0"

| 0

| 1

| SSM-suppression

| 2

| TOD-clock-sync control

| 3

| Low-address-protection control

| 4

| Extraction-authority control

| 5

| Secondary-space control

| 6

| Fetch-protection-override control

| 7

| Storage-protection-override control

| 8-12

| Translation format

| 13

| AFP-register control

| 14

| Vector control

| 15

| Address-space-function control

| 16

| Malfunction-alert subclass mask

| 17

| Emergency-signal subclass mask

| 18

| External-call subclass mask

| 19

| TOD-clock sync-check subclass mask

| 0

| 20

| Clock-comparator subclass mask

| 21

| CPU-timer subclass mask

| 22

| Service-signal subclass mask

| 24

| Set to 1

| 25

| Interrupt-key subclass mask

| 26

| Set to 1

| 27

| ETR subclass mask

| 28

| Program-call-fast

| 29

| Crypto control

| 0

| Primary space-switch-event control

| 1-19

| Primary segment-table origin

| 22

| Primary subspace-group control

| 23

| Primary private-space control

| 24

| Primary storage-alteration-event control

id="ESA/390 CR1"

| 1

|25-31

| Primary segment-table length

id="ESA/390 CR2"

| 2

| 1-25

| Dispatchable-unit-control-table origin

id="ESA/390 CR3"

| 3

| 0-15

| PSW-key mask

| 16-31

| Secondary ASN

id="ESA/390 CR4"

| 4

| 0-15

| Authorization index

id="ESA/390 CR4"

| 4

| 16-31

| Primary ASN

id="ESA/390 CR5"

| 5

| 0

| Subsystem-linkage control

| 1-24

| Linkage-table origin

| 25-31

| Linkage-table length

| 1-25

| When the address-space-function control is one,
Primary-ASN-second-table-entry

id="ESA/390 CR6"

| 6

| 0-7

| I/O-interruption subclass mask

id="ESA/390 CR7"

| 7

| 1-19

| Secondary segment-table origin

| 22

| Secondary subspace-group control

| 23

| Secondary private-space control

| 24

| Secondary storage-alteration-event control

| 25-31

| Secondary segment-table length

id="ESA/390 CR8"

| 8

| 0-15

| Extended authorization index

| 16-31

| Monitor masks

id="ESA/390 CR9"

| 9

| 0

| Successful-branching-event mask

| 1

| Instruction-fetching-event mask

| 2

| Storage-alteration-event mask

| 3

| GR-alteration-event mask

| 4

| Store-using-real-address-event mask

| 8

| Branch-address control

| 10

| Storage-alteration-space control

| 16-31

| PER general-register masks

id="ESA/390 CR10"

| 10

| 1-31

| PER starting address

id="ESA/390 CR11"

| 11

| 1-31

| PER ending address

id="ESA/390 CR12"

| 12

| 0

| Branch-trace control

| 1-29

| Trace-entry address

| 30

| ASN-trace control

| 31

| Explicit-trace control

id="ESA/390 CR13"

| 13

| 0

| Home space-switch-event control

| 1-19

|Home segment-table origin

| 23

| Home private-space control

| 24

| Home storage-alteration-event control

| 25-31

| Home segment-table length

id="ESA/390 CR14"

| 14

| 0

| Set to 1

| 1

| Set to 1

| 2

| Extended-save-area control

| 3

|Channel-report-pending subclass mask

| 4

| Recovery subclass mask

| 5

| Degradation subclass mask

| 6

| External-damage subclass mask

| 7

| Warning subclass mask

| 10

| TOD-clock-control-override control

| 12

| ASN-translation control

| 13-31

| ASN-first-table origin

id="ESA/390 CR15"

| 15

| 1-28

| Linkage-stack-entry address

Control registers in IBM z/Architecture

The control registers of z/Architecture{{sfn|z/Architecture}} are an evolutionary enhancement to the control registers of the earlier ESA/390 on the IBM S/390 processors. For details on which fields are dependent on specific features, consult the Principles of Operation.{{sfn

| z/Architecture

| pp = [https://www.vm.ibm.com/library/other/22783213.pdf#page=209 4-9–4-12]

| loc = Control Registers

}}

Because z/Architecture expands the control registers from 32 bits to 64, the bit numbering differs from that in ESA/390.

class="wikitable"

|+ z/Architecture mode control registers

! CR !! bits !! Field

id="z/Architecture CR0"

| 0

| 8

| Transactional-execution control

| 9

| Transactional-execution program-interruption filtering override

| 10

| Clock-comparator sign control

| 13

| Cryptography counter control

| 14

| Processor-activity-instrumentation-extension control

| 15

| Measurement-counter-extraction-authorization control

| 30

| Warning-track subclass mask

| 32

| TRACE TOD-clock control

| 33

| SSM-suppression

| 34

| TOD-clock-sync control

| 35

| Low-address-protection control

| 36

| Extraction-authority control

| 37

| Secondary-space control

| 38

| Fetch-protection-override control

| 39

| Storage-protection-override control

| 40

| Enhanced-DAT-enablement control

| 43

| Instruction-execution-protection-enablement control

| 44

| ASN-and-LX-reuse control

| 45

| AFP-register control

| 46

| Vector enablement control

| 48

| Malfunction-alert subclass mask

| 48

| Malfunction-alert subclass mask

| 49

| Emergency-signal subclass mask

| 50

| External-call subclass mask

| 52

| Clock-comparator subclass mask

| 0

| 53

| CPU-timer subclass mask

| 54

| Service-signal subclass mask

| 56

| Initialized to 1

| 57

| Interrupt-key subclass mask

| 58

| Measurement-alert subclass mask

| 59

| Timing-alert subclass mask

| 61

| Crypto control

id="z/Architecture CR1"

| 1

| 0-51

| Primary Address-Space Control Element (ASCE)
Primary region-table origin
Primary segment-table origin
Primary real-space token origin

| 54

| Primary subspace-group control

| 55

| Primary private-space control

| 56

| Primary storage-alteration-event

| 57

| Primary space-switch-event control

| 58

| Primary real-space control

| 60-61

| Primary designation-type control

| 62-63

| Primary table length

id="z/Architecture CR2"

| 2

| 33-57

| Dispatchable-unit-control-table origin

| 59

| Guarded-storage-facility enablement control

| 61

| Transaction diagnostic scope

| 62-63

| Transaction diagnostic control

id="z/Architecture CR3"

| 3

| 0-31

| Secondary ASN-second-table-entry instance number

| 32-47

| PSW-key mask

| 48-63

| Secondary ASN

id="z/Architecture CR4"

| 4

| 0-31

| Primary ASN-second-table-entry instance number

| 32-47

| Authorization index

id="z/Architecture CR4"

| 4

| 48-63

| Primary ASN

id="z/Architecture CR5"

| 5

| 33-57

| Primary-ASN-second-table-entry origin

id="z/Architecture CR6"

| 6

| 32-39

| I/O-interruption subclass mask

id="z/Architecture CR7"

| 7

| 0-51

| Secondary Address-Space Control Element (ASCE)
Secondary region-table origin
Secondary segment-table origin
Secondary real-space token origin

| 54

| Secondary subspace-group control

| 55

| Secondary private-space control

| 56

| Secondary storage-alteration-event control

| 58

| Secondary real-space control

| 60-61

| Secondary designation-type control

| 62-63

| Secondary table length

id="z/Architecture CR8"

| 8

| 16-31

| Enhanced-monitor masks

| 32-47

| Extended authorization index

| 48-63

| Monitor masks

id="z/Architecture CR9"

| 9

| 32

| Successful-branching-event mask

| 33

| Instruction-fetching-event mask

| 34

| Storage-alteration-event mask

| 35

| Storage-key-alteration-event mask

| 36

| Store-using-real-address-event mask

| 37

| Zero-address-detection-event mask

| 38

| Transaction-end event mask

| 39

| Instruction-fetching-nullification-event mask

| 40

| Branch-address control

| 41

| PER-event-suppression control

| 43

| Storage-alteration-space control

id="z/Architecture CR10"

| 10

| 0-63

| PER starting address

id="z/Architecture CR11"

| 11

| 0-63

| PER ending address

id="z/Architecture CR12"

| 12

| 0

| Branch-trace control

| 1

| Mode-trace control

| 2-61

| Trace-entry address

| 62

| ASN-trace control

| 63

| Explicit-trace control

id="z/Architecture CR13"

| 13

| 0-51

| Home Address-Space Control Element (ASCE)
Home region-table origin
Home segment-table origin
Home real-space token origin

| 55

| Home private-space control

| 56

| Home storage-alteration-eventl

| 57

| Home space-switch-event control

| 58

| Secondary real-space control

| 60-61

| Home designation-type control

| 62-63

| Home table length

id="z/Architecture CR14"

| 14

| 32

| Set to 1

| 33

| Set to 1

| 34

| Extended save-area control (ESA/390-compatibility mode

only)

| 35

|Channel-report-pending subclass mask

| 36

| Recovery subclass mask

| 37

| Degradation subclass mask

| 38

| External-damage subclass mask

| 39

| Warning subclass mask

| 42

| TOD-clock-control-override control

| 44

| ASN-translation control

| 45-63

| ASN-first-table origin

id="z/Architecture CR15"

| 15

| 0-60

| Linkage-stack-entry address

Control registers in Intel [[x86]] series

=CR0=

The CR0 register is 32 bits long on the 386 and higher processors. On x64 processors in long mode, it (and the other control registers) is 64 bits long. CR0 has various control flags that modify the basic operation of the processor. Register CR0 is the 32 Bit version of the old Machine Status Word (MSW) register. The MSW register was expanded to the Control Register with the appearance of the i386 processor.

class="wikitable" ! Bit !! Name !! Full Name !! Description
0	PE	Protected Mode Enable	If 1, system is in protected mode, else, system is in real mode
1	MP	Monitor co-processor	Controls interaction of WAIT/FWAIT instructions with TS flag in CR0
2	EM	Emulation	If set, no x87 floating-point unit present, if clear, x87 FPU present
3	TS	Task switched	Allows saving x87 task context upon a task switch only after x87 instruction used
4	ET	Extension type	On the 386, it allowed to specify whether the external math coprocessor was an 80287 or 80387
5	NE	Numeric error	Enable internal x87 floating point error reporting when set, else enables PC style x87 error detection
16	WP	Write protect	When set, the CPU cannot write to read-only pages when privilege level is 0
18	AM	Alignment mask	Alignment check enabled if AM set, AC flag (in EFLAGS register) set, and privilege level is 3
29	NW	Not-write through	Globally enables/disable write-through caching
30	CD	Cache disable	Globally enables/disable the memory cache
31	PG	Paging	If 1, enable paging and use the {{Section link	CR3}} register, else disable paging.

=CR1=

Reserved, the CPU will throw a #UD exception when trying to access it.

=CR2=

Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the address the program attempted to access is stored in the CR2 register.

=CR3=

Image:X86 Paging 4K.svg pages]]

Used when virtual addressing is enabled, hence when the PG bit is set in CR0. CR3 enables the processor to translate linear addresses into physical addresses by locating the page directory and page tables for the current task. Typically, the upper 20 bits of CR3 become the page directory base register (PDBR), which stores the physical address of the first page directory. If the PCIDE bit in CR4 is set, the lowest 12 bits are used for the process-context identifier (PCID).{{cite book |title=Intel 64 and IA-32 Architectures Software Developer's Manual |volume=3A: System Programming Guide, Part 1 |section=4.10.1 Process-Context Identifiers (PCIDs) |author=Intel Corporation |year=2016 |url=https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf}}

=CR4=

Used in protected mode to control operations such as virtual-8086 support, enabling I/O breakpoints, page size extension and machine-check exceptions.

class="wikitable" ! Bit !! Name !! Full Name !! Description
0	VME	Virtual 8086 Mode Extensions	If set, enables support for the virtual interrupt flag (VIF) in virtual-8086 mode.
1	PVI	Protected-mode Virtual Interrupts	If set, enables support for the virtual interrupt flag (VIF) in protected mode.
2	TSD	Time Stamp Disable	If set, RDTSC instruction can only be executed when in ring 0, otherwise RDTSC can be used at any privilege level.
3	DE	Debugging Extensions	If set, enables debug register based breaks on I/O space access.
4	PSE	Page Size Extension	If set, enables 32-bit paging mode to use 4 MiB huge pages in addition to 4 KiB pages. If PAE is enabled or the processor is in x86-64 long mode this bit is ignored.{{cite web \| url=http://developer.amd.com/wordpress/media/2012/10/24593_APM_v2.pdf \| title=AMD64 Architecture Programmer's Manual Volume 2: System Programming \| publisher=AMD \| date=September 2012 \| pages=127 & 130 \| access-date=2017-08-04}}
5	PAE	Physical Address Extension	If set, changes page table layout to translate 32-bit virtual addresses into extended 36-bit physical addresses.
6	MCE	Machine Check Exception	If set, enables machine check interrupts to occur.
7	PGE	Page Global Enabled	If set, address translations (PDE or PTE records) may be shared between address spaces.
8	PCE	Performance-Monitoring Counter enable	If set, RDPMC can be executed at any privilege level, else RDPMC can only be used in ring 0.
9	OSFXSR	Operating system support for FXSAVE and FXRSTOR instructions	If set, enables Streaming SIMD Extensions (SSE) instructions and fast FPU save & restore.
10	OSXMMEXCPT	Operating System Support for Unmasked SIMD Floating-Point Exceptions	If set, enables unmasked SSE exceptions.
11	UMIP	User-Mode Instruction Prevention	If set, the SGDT, SIDT, SLDT, SMSW and STR instructions cannot be executed if CPL > 0.
12	LA57	57-Bit Linear Addresses	If set, enables 5-Level Paging.{{cite web \| url=https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf \| title=5-Level Paging and 5-Level EPT \| publisher=Intel \| date=May 2017 \| page=16 \| access-date=2018-01-23}}{{cite web \| url = https://software.intel.com/content/dam/develop/external/us/en/documents-tps/253668-sdm-vol-3a.pdf \| title = Intel 64 and IA-32 Architectures Software Developer's Manual \| volume = 3A \| publisher = Intel® Corporation \| date = 2021-06-28 \| access-date = 2021-09-21 }}{{rp\|2–18}}
13	VMXE	Virtual Machine Extensions Enable	see Intel VT-x x86 virtualization.
14	SMXE	Safer Mode Extensions Enable	see Trusted Execution Technology (TXT)
15	{{n/a\|{{efn\|In early drafts of the Intel SGX specification, bit 15 of CR4 was named "CR4.SEE" and was described as an SGX enclave-instruction enable bit.Intel, [https://kib.kiev.ua/x86docs/Intel/SGX/329298-001.pdf Software Guard Extensions Programming Reference], ref no. 329298-001, sep 2013 - chapters 1.7 and 6.5.2 describe CR4.SEE. Later revisions of this specification removed references to this bit.Intel, [https://kib.kiev.ua/x86docs/Intel/SGX/329298-001.pdf Software Guard Extensions Programming Reference], ref no. 329298-002, oct 2014 - makes no mention of CR4.SEE.\|group=IntelCR4}}}}	{{n/a\|(Reserved)}}	{{n/a}}
16	FSGSBASE	FSGSBASE Enable	If set, enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
17	PCIDE	PCID Enable	If set, enables process-context identifiers (PCIDs).
18	OSXSAVE	XSAVE and Processor Extended States Enable
19	KL	Key Locker Enable	If set, enables the AES Key Locker instructions.
20	{{Visible anchor\|SMEP}}{{cite web \| url = https://www.ncsi.com/nsatc11/presentations/wednesday/emerging_technologies/fischer.pdf \| title = Supervisor Mode Execution Protection \| first = Stephen \| last = Fischer \| date = 2011-09-21 \| work = NSA Trusted Computing Conference 2011 \| publisher = National Conference Services, Inc. \| archive-url = https://web.archive.org/web/20160803075007/https://www.ncsi.com/nsatc11/presentations/wednesday/emerging_technologies/fischer.pdf \| archive-date = 2016-08-03 \| url-status = dead \| access-date = 2017-08-04 }}	Supervisor Mode Execution Protection Enable	If set, execution of code in a higher ring generates a fault.
21	SMAP	Supervisor Mode Access Prevention Enable	If set, access of data in a higher ring generates a fault.{{cite web \| title=x86: Supervisor Mode Access Prevention \| url=https://lwn.net/Articles/517251/ \| last=Anvin \| first=H. Peter \| date=2012-09-21 \| publisher=LWN.net \| access-date=2017-08-04}}
22	PKE	Protection Key Enable	See Intel 64 and IA-32 Architectures Software Developer's Manual.
23	CET	Control-flow Enforcement Technology	If set, enables control-flow enforcement technology.{{rp\|2–19}}
24	PKS	Enable Protection Keys for Supervisor-Mode Pages	If set, each supervisor-mode linear address is associated with a protection key when 4-level or 5-level paging is in use.{{rp\|2–19}}
25	UINTR	User Interrupts Enable	If set, enables user-mode inter-processor interrupts and their associated instructions and data structures.
63-26	{{n/a}}	{{n/a\|(Reserved)}}	{{n/a}}

=CR5–7=

Reserved, same case as CR1.

Additional Control registers in Intel [[x86-64]] series

=EFER=

Extended Feature Enable Register (EFER) is a model-specific register added in the AMD K6 processor, to allow enabling the SYSCALL/SYSRET instruction, and later for entering and exiting long mode. This register becomes architectural in AMD64 and has been adopted by Intel as IA32_EFER. Its MSR number is 0xC0000080.

class="wikitable" border="1"
Bit ! Purpose
0 \| SCE (System Call Extensions)
1 \| DPE (AMD K6 only: Data Prefetch Enable)
2 \| SEWBED (AMD K6 only: Speculative EWBE# Disable)
3 \| GEWBED (AMD K6 only: Global EWBE# Disable)
4 \| L2D (AMD K6 only: L2 Cache Disable)
5-7 \| Reserved, Read as Zero
8 \| LME (Long Mode Enable)
9 \| Reserved
10 \| LMA (Long Mode Active)
11 \| NXE (No-Execute Enable)
12 \| SVME (Secure Virtual Machine Enable)
13 \| LMSLE (Long Mode Segment Limit Enable)
14 \| FFXSR (Fast FXSAVE/FXRSTOR)
15 \| TCE (Translation Cache Extension)
16 \| Reserved
17 \| MCOMMIT (MCOMMIT instruction enable)
18 \| INTWB (Interruptible WBINVD/WBNOINVD enable)
19 \| Reserved
20 \| UAIE (Upper Address Ignore Enable)
21 \| AIBRSE (Automatic IBRS Enable)
22–63 \| Reserved

class="wikitable" border="1"

Bit

! Purpose

| SCE (System Call Extensions)

| DPE (AMD K6 only: Data Prefetch Enable)

| SEWBED (AMD K6 only: Speculative EWBE# Disable)

| GEWBED (AMD K6 only: Global EWBE# Disable)

| L2D (AMD K6 only: L2 Cache Disable)

5-7

| Reserved, Read as Zero

| LME (Long Mode Enable)

| Reserved

| LMA (Long Mode Active)

| NXE (No-Execute Enable)

| SVME (Secure Virtual Machine Enable)

| LMSLE (Long Mode Segment Limit Enable)

| FFXSR (Fast FXSAVE/FXRSTOR)

| TCE (Translation Cache Extension)

| Reserved

| MCOMMIT (MCOMMIT instruction enable)

| INTWB (Interruptible WBINVD/WBNOINVD enable)

| Reserved

| UAIE (Upper Address Ignore Enable)

| AIBRSE (Automatic IBRS Enable)

22–63

| Reserved

=CR8=

CR8 is a new register accessible in 64-bit mode using the REX prefix. CR8 is used to prioritize external interrupts and is referred to as the task-priority register (TPR).

The AMD64 architecture allows software to define up to 15 external interrupt-priority classes. Priority classes are numbered from 1 to 15, with priority-class 1 being the lowest and priority-class 15 the highest. CR8 uses the four low-order bits for specifying a task priority and the remaining 60 bits are reserved and must be written with zeros.

System software can use the TPR register to temporarily block low-priority interrupts from interrupting a high-priority task. This is accomplished by loading TPR with a value corresponding to the highest-priority interrupt that is to be blocked. For example, loading TPR with a value of 9 (1001b) blocks all interrupts with a priority class of 9 or less, while allowing all interrupts with a priority class of 10 or more to be recognized. Loading TPR with 0 enables all external interrupts. Loading TPR with 15 (1111b) disables all external interrupts.

The TPR is cleared to 0 on reset.

=XCR0 and XSS=

XCR0, or Extended Control Register 0, is a control register which is used to toggle the storing or loading of registers related to specific CPU features using the XSAVE/XRSTOR instructions. It is also used with some features to enable or disable the processor's ability to execute their corresponding instructions. It can be changed using the privileged XSETBV read using the unprivileged XGETBV instructions.{{cite web |title=Chapter 13, Managing State Using The Xsave Feature Set |url=https://software.intel.com/sites/default/files/managed/a4/60/253665-sdm-vol-1.pdf |website=Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture |publisher=Intel Corporation (2019) |access-date=23 March 2019}}

class="wikitable" border="1"
Bit ! Name ! Enabled Feature ! Purpose
0 \| X87 \| x87 FPU \| x87 FPU/MMX State, must be '1'
1 \| SSE \| SSE \| MXCSR and 16 XMM registers
2 \| AVX \| AVX \| 16 upper-halves of the YMM registers{{efn\|The lower 128 bits of all YMM registers is stored in the SSE state.}}
3 \| BNDREG \| rowspan="2" \| MPX \| Four BND registers
4 \| BNDCSR \| BNDCFGU and BNDSTATUS registers
5 \| OPMASK \| rowspan="3" \| AVX-512 \| Eight k-mask registers
6 \| ZMM_Hi256 \| 16 upper-halves of the ZMM registers{{efn\|The lower 256 bits of ZMM registers ZMM0 through ZMM15 are stored in the SSE and AVX states.}}
7 \| Hi16_ZMM \| 16 "high" ZMM registers (ZMM16 through ZMM31)
8 \| PT \| Processor Trace \|
9 \| PKRU \| Protection Keys \| PKRU register
10 \| PASID \| \|
11 \| CET_U \| rowspan="2" \| Intel CET \| User shadow stack
12 \| CET_S \| Supervisor shadow stack
13 \| HDC \| Hardware Duty Cycling \|
14 \| UINTR \| User interrupts \|
15 \| LBR \| Last Branch Records \|
16 \| HWP \| Hardware P-states \|
17 \| XTILECFG \| rowspan="2" \| Intel AMX \| 64-byte TILECFG register
18 \| XTILEDATA \| Eight 1024-byte TILE registers
19{{efn\|Even though Intel APX is indicated through bit 19 of XCR0, it is actually written, through XSAVE (the uncompacted form), in the unused 128 byte space left where Intel MPX went.}} \| APX \| Intel APX \| 16 "high" GPRs (R16 through R31)
20–63 \| colspan="3" \| Reserved

class="wikitable" border="1"

Bit

! Name

! Enabled Feature

! Purpose

| X87

| x87 FPU

| x87 FPU/MMX State, must be '1'

| SSE

| MXCSR and 16 XMM registers

| AVX

| 16 upper-halves of the YMM registers{{efn|The lower 128 bits of all YMM registers is stored in the SSE state.}}

| BNDREG

| rowspan="2" | MPX

| Four BND registers

| BNDCSR

| BNDCFGU and BNDSTATUS registers

| OPMASK

| rowspan="3" | AVX-512

| Eight k-mask registers

| ZMM_Hi256

| 16 upper-halves of the ZMM registers{{efn|The lower 256 bits of ZMM registers ZMM0 through ZMM15 are stored in the SSE and AVX states.}}

| Hi16_ZMM

| 16 "high" ZMM registers (ZMM16 through ZMM31)

| PT

| Processor Trace

| PKRU

| Protection Keys

| PKRU register

| PASID

| CET_U

| rowspan="2" | Intel CET

| User shadow stack

| CET_S

| Supervisor shadow stack

| HDC

| Hardware Duty Cycling

| UINTR

| User interrupts

| LBR

| Last Branch Records

| HWP

| Hardware P-states

| XTILECFG

| rowspan="2" | Intel AMX

| 64-byte TILECFG register

| XTILEDATA

| Eight 1024-byte TILE registers

19{{efn|Even though Intel APX is indicated through bit 19 of XCR0, it is actually written, through XSAVE (the uncompacted form), in the unused 128 byte space left where Intel MPX went.}}

| APX

| Intel APX

| 16 "high" GPRs (R16 through R31)

20–63

| colspan="3" | Reserved

There is also the IA32_XSS MSR, which is located at address DA0h. The IA32_XSS MSR controls bits of XCR0 which are considered to be "supervisor" state, and should be invisible to regular programs. It operates with the privileged XSAVES and XRSTORS instructions by adding supervisor state to the data they operate with. Put simply, if the X87 state was enabled in XCR0 and PT state was enabled in IA32_XSS, the XSAVE instruction would only store X87 state, while the privileged XSAVES would store both X87 and PT states. Because it is an MSR, it can be accessed using the RDMSR and WRMSR instructions.

class="wikitable" border="1"
Bit ! Purpose
0–7 \| Reserved; must be 0.
8 \| PT (Enables the saving and loading of nine Processor Trace MSRs.)
10 \| Processor Address Space ID (PASID) state
11 \| Control-flow Enforcement Technology (CET) User State
12 \| Control-flow Enforcement Technology (CET) Supervisor State
13 \| HDC (Enables the saving and loading of the IA32_PM_CTL1 MSR.)
14 \| User interrupts (UINTR) state
15 \| Last branch recording (LBR) state
16 \| HWP (enables the saving/loading of IA32_HWP_REQUEST MSR)
17–63 \| Reserved; must be 0.

class="wikitable" border="1"

Bit

! Purpose

0–7

| Reserved; must be 0.

| PT (Enables the saving and loading of nine Processor Trace MSRs.)

| Processor Address Space ID (PASID) state

| Control-flow Enforcement Technology (CET) User State

| Control-flow Enforcement Technology (CET) Supervisor State

| HDC (Enables the saving and loading of the IA32_PM_CTL1 MSR.)

| User interrupts (UINTR) state

| Last branch recording (LBR) state

| HWP (enables the saving/loading of IA32_HWP_REQUEST MSR)

17–63

| Reserved; must be 0.

Notes

References

;IBM manuals

:;M67prelim

::{{cite book

| title = System/360 Model 67 - Time Sharing System - Preliminary Technical Summary

| id = C20-1647-0

| ref = {{sfnref|M67prelim}}

| edition = First

| url = http://bitsavers.org/pdf/ibm/360/model67/C20-1647-0_System_360_Model_67_Time_Sharing_System_Preliminary_Technical_Summary_1966.pdf

| publisher = IBM

| series = Systems Reference Library

| access-date = May 8, 2023

}}

:;M67

::{{cite book

| title = IBM System/360 Model 67 - Functional Characteristics

| id = A27-2719-0

| ref = {{sfnref|M67}}

| date = February 1972

| edition = Third

| url = http://bitsavers.org/pdf/ibm/360/functional_characteristics/GA27-2719-2_360-67_funcChar.pdf

| publisher = IBM

| series = Systems Reference Library

| access-date = May 8, 2023

}}

:;S/370

::{{cite book

| title = IBM System/370 - Principles of Operation

| id = GA22-7000-10

| ref = {{sfnref|S/370}}

| date = September 1987

| edition = Eleventh

| url = http://bitsavers.org/pdf/ibm/36http://bitsavers.org/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf

| publisher = IBM

| access-date = May 8, 2023

}}

:;S/370-XA

::{{cite book

| title = IBM System/370 Extended Architecture Principles of Operation

| id = SA22-7085-1

| date = January 1987

| edition = Second

| url = http://bitsavers.org/pdf/ibm/370/princOps/SA22-7085-1_370-XA_Principles_of_Operation_Jan87.pdf

| ref = {{sfnref|S/370-XA}}

| publisher = IBM

| access-date = May 8, 2023

}}

:;S/370-ESA

:{{cite book

| title = IBM Enterprise Systems Architecture/370 Principles of Operation

| id = SA22-7200-0

| date = August 1988

| edition = First

| url = http://bitsavers.org/pdf/ibm/370/princOps/SA22-7200-0_370-ESA_Principles_of_Operation_Aug88.pdf

| ref = {{sfnref|S/370-ESA}}

| publisher = IBM

| access-date = May 8, 2023

}}

:;S/390-ESA

::{{cite book

| title = IBM Enterprise Systems Architecture/390 Principles of Operation

| id = SA22-7201-08

| date = June 2003

| edition = Ninth

| url = https://publibz.boulder.ibm.com/epubs/pdf/dz9ar008.pdf

| ref = {{sfnref|S/390-ESA}}

| publisher = IBM

| access-date = May 8, 2023

}}

:;z/Architecture

::{{cite book

| title = z/Architecture - Principles of Operation

| id = SA22-7832-13

| date = May 2022

| edition = Fourteenth

| url = https://www.vm.ibm.com/library/other/27493840.pdf

| ref = {{sfnref|z/Architecture}}

| publisher = IBM

| access-date = May 8, 2023

}}

External links

[https://www.intel.com/design/processor/manuals/253668.pdf Intel 64 and IA-32 Architectures Developer's Manual: Vol. 3A]
[https://software.intel.com/en-us/articles/intel-sdm Intel 64 and IA-32 Architectures Software Developer Manuals]
[https://support.amd.com/en-us/search/tech-docs#k=AMD64 Tech Docs: AMD64]
[https://www.gamedeveloper.com/programming/wyatt-s-world-cracking-open-the-pentium-iii Wyatt's World: Cracking Open the Pentium III] (1999-05-28)

Category:Operating system technology

Category:Central processing unit

Category:Digital registers

Control register

History

Control registers in IBM 360/67

= M67 CR0 =

= M67 CR2 =

= M67 CR4 =

= M67 CR5 =

= M67 CR6 =

= M67 CR8 =

= M67 CR9 =

= M67 CR10 =

= M67 CR11 =

= M67 CR12 =

= M67 CR13 =

= M67 CR14 =

Control registers in IBM S/390

Control registers in IBM z/Architecture

Control registers in Intel [[x86]] series

=CR0=

=CR1=

=CR2=

=CR3=

=CR4=

=CR5–7=

Additional Control registers in Intel [[x86-64]] series

=EFER=

=CR8=

=XCR0 and XSS=

See also

Notes

References

External links