Don't-care term

Examples of don't-care terms are the binary values 1010 through 1111 (10 through 15 in decimal) for a function that takes a binary-coded decimal (BCD) value, because a BCD value never takes on such values (so called pseudo-tetrades); in the pictures, the circuit computing the lower left bar of a 7-segment display can be minimized to {{nowrap|{{overline|a}} b + {{overline|a}} {{overline|c}}}} by an appropriate choice of circuit outputs for {{nowrap|dcba {{=}} 1010…1111}}.

Write-only registers, as frequently found in older hardware, are often a consequence of don't-care optimizations in the trade-off between functionality and the number of necessary logic gates.

Don't-care states can also occur in encoding schemes and communication protocols.

"Don't care" may also refer to an unknown value in a multi-valued logic system, in which case it may also be called an X value or don't know. In the Verilog hardware description language such values are denoted by the letter "X". In the VHDL hardware description language such values are denoted (in the standard logic package) by the letter "X" (forced unknown) or the letter "W" (weak unknown).

An X value does not exist in hardware. In simulation, an X value can result from two or more sources driving a signal simultaneously, or the stable output of a flip-flop not having been reached. In synthesized hardware, however, the actual value of such a signal will be either 0 or 1, but will not be determinable from the circuit's inputs.

Further considerations are needed for logic circuits that involve some feedback. That is, those circuits that depend on the previous output(s) of the circuit as well as its current external inputs. Such circuits can be represented by a state machine. It is sometimes possible that some states that are nominally can't-happen conditions can accidentally be generated during power-up of the circuit or else by random interference (like cosmic radiation, electrical noise or heat). This is also called forbidden input. In some cases, there is no combination of inputs that can exit the state machine into a normal operational state. The machine remains stuck in the power-up state or can be moved only between other can't-happen states in a walled garden of states. This is also called a hardware lockup or soft error. Such states, while nominally can't-happen, are not don't-care, and designers take steps either to ensure that they are really made can't-happen, or else if they do happen, that they create a don't-care alarm indicating an emergency state for error detection, or they are transitory and lead to a normal operational state.

• Decision table
• Side effect
• Short-circuit evaluation
• Incomplete address decoding
• Incomplete opcode decoding
• Logic redundancy
• Undefined behaviour
• Undefined variable
• Uninitialized variable
• Four-valued logic
• Nine-valued logic

{{Reflist|group="nb"|refs=

Examples of encoding schemes with don't-care states include Hertz encoding, Chen–Ho encoding and Densely packed decimal (DPD).

}}

{{Reflist|refs=

{{cite book |title=The Design Of Switching Circuits |author-first1=William |author-last1=Keister |author-first2=Alistair E. |author-last2=Ritchie |author-first3=Seth H. |author-last3=Washburn |date=1951 |edition=1 |publisher=D. Van Nostrand Company, Inc. |series=The Bell Telephone Laboratories Series |page=[https://archive.org/details/TheDesignOfSwitchingCircuits/page/n170 147] |url=https://archive.org/details/TheDesignOfSwitchingCircuits |access-date=2020-05-09 |url-status=live |archive-url=https://web.archive.org/web/20200509143306/https://archive.org/details/TheDesignOfSwitchingCircuits/page/n537/mode/2up |archive-date=2020-05-09}} [https://archive.org/details/TheDesignOfSwitchingCircuits] (2+xx+556+2 pages)

{{cite book |title=Synthesis of electronic computing and control circuits |orig-date=January 1951 |date=1952 |edition=second printing, revised |author-first1=Howard H. |author-last1=Aiken |author-link1=Howard H. Aiken |author-first2=Gerrit |author-last2=Blaauw |author-link2=Gerrit Blaauw |author-first3=William |author-last3=Burkhart |author-first4=Robert J. |author-last4=Burns |author-first5=Lloyd |author-last5=Cali |author-first6=Michele |author-last6=Canepa |author-first7=Carmela M. |author-last7=Ciampa |author-first8=Charles A. |author-last8=Coolidge, Jr. |author-first9=Joseph R. |author-last9=Fucarile |author-first10=J. Orten |author-last10=Gadd, Jr. |author-first11=Frank F. |author-last11=Gucker |author-first12=John A. |author-last12=Harr |author-first13=Robert L. |author-last13=Hawkins |author-first14=Miles V. |author-last14=Hayes |author-first15=Richard |author-last15=Hofheimer |author-first16=William F. |author-last16=Hulme |author-first17=Betty L. |author-last17=Jennings |author-first18=Stanley A. |author-last18=Johnson |author-first19=Theodore |author-last19=Kalin |author-first20=Marshall |author-last20=Kincaid |author-first21=E. Edward |author-last21=Lucchini |author-first22=William |author-last22=Minty |author-first23=Benjamin L. |author-last23=Moore |author-first24=Joseph |author-last24=Remmes |author-first25=Robert J. |author-last25=Rinn |author-first26=John W. |author-last26=Roche |author-first27=Jacquelin |author-last27=Sanbord |author-first28=Warren L. |author-last28=Semon |author-first29=Theodore |author-last29=Singer |author-first30=Dexter |author-last30=Smith |author-first31=Leonard |author-last31=Smith |author-first32=Peter F. |author-last32=Strong |author-first33=Helene V. |author-last33=Thomas |author-first34=An |author-last34=Wang |author-link34=An Wang |author-first35=Martha L. |author-last35=Whitehouse |author-first36=Holly B. |author-last36=Wilkins |author-first37=Robert E. |author-last37=Wilkins |author-first38=Way Dong |author-last38=Woo |author-first39=Elbert P. |author-last39=Little |author-first40=M. Scudder |author-last40=McDowell |location=Write-Patterson Air Force Base |publisher=Harvard University Press (Cambridge, Massachusetts, USA) / Geoffrey Cumberlege Oxford University Press (London) |volume=XXVII |series=The Annals of the Computation Laboratory of Harvard University |id=ark:/13960/t4zh1t09d |url=https://archive.org/stream/in.ernet.dli.2015.509288/2015.509288.Synthesis-Of#page/n6/mode/1up |access-date=2017-04-16}} (2+x+278+2 pages) (NB. Work commenced in April 1948.)

{{cite journal |author-last=Karnaugh |author-first=Maurice |author-link=Maurice Karnaugh |title=The Map Method for Synthesis of Combinational Logic Circuits |journal=Transactions of the American Institute of Electrical Engineers, Part I: Communication and Electronics |volume=72 |issue=5 |pages=593–599 |date=November 1953 |orig-date=1953-04-23, 1953-03-17 |id=Paper 53-217 |doi=10.1109/TCE.1953.6371932 |s2cid=51636736 |url=http://philectrosophy.com/documents/The%20Map%20Method%20For%20Synthesis%20of.pdf |access-date=2017-04-16 |url-status=dead |archive-url=https://web.archive.org/web/20170416232229/http://philectrosophy.com/documents/The%20Map%20Method%20For%20Synthesis%20of.pdf |archive-date=2017-04-16}} (7 pages)

{{cite journal |title=Optimized Data Encoding for Digital Computers |author-last=Kautz |author-first=William H. |author-link=William H. Kautz |journal=Convention Record of the I.R.E., 1954 National Convention, Part 4 - Electronic Computers and Information Theory |publisher=I.R.E. |series=Session 19: Information Theory III - Speed and Computation |date=June 1954 |location=Stanford Research Institute, Stanford, California, USA |pages=47–57 |url=https://worldradiohistory.com/Archive-IRE/50s/IRE-1954-Part-4-Electronic-Computers-&-Information%20pdf |access-date=2020-07-03 |url-status=live |archive-url=https://web.archive.org/web/20200703180632/https://worldradiohistory.com/Archive-IRE/50s/IRE-1954-Part-4-Electronic-Computers-%26-Information%20pdf |archive-date=2020-07-03}} [https://web.archive.org/web/20200703173707/https://worldradiohistory.com/hd2/IDX-Site-Technical/Engineering-General/Archive-IRE-IDX/IDX/50s/IRE-1954-Part-4-Electronic-Computers-%26-Information-OCR-Page-0049.pdf][https://web.archive.org/web/20200703175038/https://worldradiohistory.com/hd2/IDX-Site-Technical/Engineering-General/Archive-IRE-IDX/IDX/50s/IRE-1954-Part-4-Electronic-Computers-%26-Information-OCR-Page-0050.pdf][https://web.archive.org/web/20200703175214/https://worldradiohistory.com/hd2/IDX-Site-Technical/Engineering-General/Archive-IRE-IDX/IDX/50s/IRE-1954-Part-4-Electronic-Computers-%26-Information-OCR-Page-0051.pdf][https://web.archive.org/web/20200703175243/https://worldradiohistory.com/hd2/IDX-Site-Technical/Engineering-General/Archive-IRE-IDX/IDX/50s/IRE-1954-Part-4-Electronic-Computers-%26-Information-OCR-Page-0052.pdf][https://web.archive.org/web/20200703175313/https://worldradiohistory.com/hd2/IDX-Site-Technical/Engineering-General/Archive-IRE-IDX/IDX/50s/IRE-1954-Part-4-Electronic-Computers-%26-Information-OCR-Page-0053.pdf][https://web.archive.org/web/20200703175344/https://worldradiohistory.com/hd2/IDX-Site-Technical/Engineering-General/Archive-IRE-IDX/IDX/50s/IRE-1954-Part-4-Electronic-Computers-%26-Information-OCR-Page-0054.pdf][https://web.archive.org/web/20200703175425/https://worldradiohistory.com/hd2/IDX-Site-Technical/Engineering-General/Archive-IRE-IDX/IDX/50s/IRE-1954-Part-4-Electronic-Computers-%26-Information-OCR-Page-0055.pdf][https://web.archive.org/web/20200703175459/https://worldradiohistory.com/hd2/IDX-Site-Technical/Engineering-General/Archive-IRE-IDX/IDX/50s/IRE-1954-Part-4-Electronic-Computers-%26-Information-OCR-Page-0056.pdf][https://web.archive.org/web/20200703175529/https://worldradiohistory.com/hd2/IDX-Site-Technical/Engineering-General/Archive-IRE-IDX/IDX/50s/IRE-1954-Part-4-Electronic-Computers-%26-Information-OCR-Page-0057.pdf][https://web.archive.org/web/20200703175606/https://worldradiohistory.com/hd2/IDX-Site-Technical/Engineering-General/Archive-IRE-IDX/IDX/50s/IRE-1954-Part-4-Electronic-Computers-%26-Information-OCR-Page-0058.pdf][https://web.archive.org/web/20200703175641/https://worldradiohistory.com/hd2/IDX-Site-Technical/Engineering-General/Archive-IRE-IDX/IDX/50s/IRE-1954-Part-4-Electronic-Computers-%26-Information-OCR-Page-0059.pdf] (11 pages)

{{cite book |title=Logical design of digital computers |author-first=Montgomery |author-last=Phister, Jr. |publisher=John Wiley & Sons Inc. |date=April 1959 |orig-date=December 1958 |edition=3rd printing, 1st |series=Digital Design and Applications |location=New York, USA |isbn=0-47168805-3 |id={{ISBN|978-0-47168805-1}} |lccn=58-6082 |mr=0093930 |page=97 |quote-page=97 |quote=[…] These prohibited combinations will here be called redundancies (they have also been called irrelevancies, "don't cares," and forbidden combinations), and they can usually be used to simplify Boolean functions. […]}} (xvi+408 pages)

{{cite book |title=Switching Circuits and Logical Design |author-first=Samuel Hawks |author-last=Caldwell |author-link=Samuel Hawks Caldwell |version=5th printing September 1963 |date=1958-12-01 |orig-date=February 1958 |edition=1st |publisher=John Wiley & Sons Inc. |publication-place=New York, USA |location=Watertown, Massachusetts, USA |isbn=0-47112969-0 |lccn=58-7896}} (xviii+686 pages)

{{cite journal |title=Samuel H. Caldwell. Switching circuits and logical design. John Wiley & Sons, Inc., New York 1958, and Chapman & Hall Limited, London 1958, xvii + 686 pp. |author-first=Edward Forrest |author-last=Moore |author-link=Edward Forrest Moore |type=Review |journal=The Journal of Symbolic Logic |volume=23 |issue=4 |date=December 1958 |doi=10.2307/2964020 |pages=433–434 |jstor=2964020 |s2cid=57495605 |quote-page=433 |quote=[…] what {{citeref|Caldwell|1958|Caldwell|style=plain}} calls "optional entries" […] other authors have called "invalid combinations", "don't cares", "vacuous combinations" […]}} (2 pages)

{{cite journal |title=Code and Code Converters - Part 2: Mapping techniques and code converters |author-first=Noel Malcolm |author-last=Morris |journal=Wireless World |date=January 1969 |orig-date=1968-12-16 |volume=75 |number=1399 |publisher=Iliffe Technical Publications Ltd. |pages=34–37 |url=https://worldradiohistory.com/UK/Wireless-World/60s/Wireless-World-1969-01.pdf |access-date=2020-05-09 |url-status=live |archive-url=https://web.archive.org/web/20210309013749/https://worldradiohistory.com/UK/Wireless-World/60s/Wireless-World-1969-01.pdf |archive-date=2021-03-09}} [https://books.google.com/books?id=FcMpAQAAMAAJ&q=Codes+Code+Converters+by+N+M+Morris]

{{cite book |title=Logic Circuits |author-first=Noel Malcolm |author-last=Morris |date=1969 |edition=1 |publisher=McGraw-Hill |series=European electrical and electronic engineering series |publication-place=London, UK |pages=31, 96, 114 |lccn=72458600 |isbn=0-07094106-8 |id={{ISBN|978-0-07094106-9}}. {{NCID|BA12104142}} |url=https://books.google.com/books?id=4T7jVPmu4OcC&q=can't+happen |access-date=2021-03-28 |quote-page=31 |quote=[…] sometimes known as a can't happen condition […]}} (x+189 pages)

{{cite journal |title=unknown |author= |journal=Colloque international / International Symposium. Systèmes logiques: Conception et applications / Design and Applications of Logical Systems. Actes / Proceedings. Bruxelles, 15–20 septembre 1969 / Brussels, September 15–20, 1969. |date=1970 |volume=Part 2 |language=en, fr |editor=Association Internationale pour le Calcul Analogique (AICA) |publisher=Presses Académiques Européennes |location=Bruxelles, Belgium |publication-date=1970 |orig-date=1969-09-15 |page=1253 |url=https://books.google.com/books?id=J2IhAQAAIAAJ&q=Can't+happen |access-date=2021-03-28}} (xxxiii+650+676 pages)

{{cite book |title=Analysis and Design of Sequential Digital Systems |chapter=2.3.7. Don't cares |author-first1=Larry Frederick |author-last1=Lind |author-first2=John Christopher Cunliffe |author-last2=Nelson |edition=1 |date=1977-04-01 |series=Electrical and Electronic Engineering |publisher=The Macmillan Press Ltd. |location=London & Basingstoke, UK |isbn=0-333-19266-4 |doi=10.1007/978-1-349-15757-0 |pages=[https://archive.org/details/AnalysisDesignOfSequentialDigitalSystems/page/n28 20], 121–122 |url=https://archive.org/details/AnalysisDesignOfSequentialDigitalSystems |chapter-url=https://books.google.com/books?id=fj1dDwAAQBAJ&pg=PA20 |access-date=2020-04-30 |url-status=live |archive-url=https://web.archive.org/web/20200430003314/https://books.google.com/books?id=fj1dDwAAQBAJ&pg=PA20&lpg=PA20 |archive-date=2020-04-30}} (4+viii+146+6 pages)

{{cite book |title=Contemporary Logic Design |chapter=Chapter 2.2.4 Incompletely Specified Functions |author-first=Randy Howard |author-last=Katz |author-link=Randy Howard Katz |date=1994 |orig-date=May 1993 |location=Berkeley, California, USA |publisher=The Benjamin/Cummings Publishing Company, Inc. |publication-place=Redwood City, California, USA |edition=1 |isbn=0-8053-2703-7 |id=32703-7 |page=64 |quote-page=64 |quote=[…] The output functions have the value "X" for each of the input combinations we should never encounter. When used in a truth tables, the value X is often called a don't care. Do not confuse this with the value X reported by many logic simulators, where it represents an undefined value or a don't know. Any actual implementation of the circuit will generate some output for the don't care cases. […]}} (2+xxviii+699+10+2 pages)

{{cite book |title=VHDL: A Logic Synthesis Approach |author-first1=David |author-last1=Naylor |author-first2=Simon |author-last2=Jones |date=May 1997 |publisher=Chapman & Hall / Cambridge University Press / Springer Science & Business Media |edition=reprint of 1st |isbn=0-412-61650-5 |pages=14–15, 219, 221 |url=https://books.google.com/books?id=qUBXxDy0p9MC&pg=PA14 |access-date=2020-03-30}} (x+327 pages)

{{cite book |editor-first=John A. |editor-last=Strong |title=Basic Digital Electronics |chapter=Chapter 2.11 Hazards and Glitches |series=Physics and Its Applications |volume=2 |pages=28–29 |publisher=Chapman & Hall / Springer Science & Business Media, B.V. |date=2013-03-12 |orig-date=1991 |edition=reprint of 1st |lccn=90-2689 |isbn=978-9-40113118-6 |chapter-url=https://books.google.com/books?id=1QToCAAAQBAJ&pg=PA28 |access-date=2020-03-30}} (220 pages)

{{cite book |title=Digital Logic Design |author-first1=Brian |author-last1=Holdsworth |author-first2=Clive |author-last2=Woods |edition=4 |date=2002 |publisher=Newnes Books / Elsevier Science |isbn=((0-7506-4588-2)) |id={{ISBN|978-0-08047730-5}} |pages=55–56, 251 |url=https://books.google.com/books?id=o7enSwSVvgYC |access-date=2020-04-19}} (519 pages) [https://web.archive.org/web/20200419213939/http://s2.bitdownload.ir/Ebook/Electronics/Holdsworth%20-%20Digital%20Logic%20Design%204e%20HQ%20(Newnes,%202002).pdf]

{{cite book |editor-first1=Ramayya |editor-last1=Kumar |editor-first2=Thomas |editor-last2=Kropf |title=Proceedings of the Second International Conference, TPCD '94, Bad Herrenalb, Germany, September 26–28, 1994. |series=Lecture Notes in Computer Science |volume=901 |edition=1st |doi=10.1007/3-540-59047-1 |isbn=978-3-540-59047-7 |issn=0302-9743 |page=136 |publisher=Springer-Verlag Berlin Heidelberg |date=1995 |s2cid=42116934 |chapter-url=https://link.springer.com/book/10.1007/3-540-59047-1 |access-date=2020-03-30 |chapter=Theorem Provers in Circuit Design}} (viii+312 pages)

{{cite book |title=Toshiba 8 Bit Microcontroller TLCS-870/C Series TMP86PM29BUG |date=2008-08-29 |orig-date=2007-10-11 |edition=2 |publisher=Toshiba Corporation |page=61 |url=https://toshiba.semicon-storage.com/info/docget.jsp?did=10942&prodName=TMP86PM29BUG&usg=AOvVaw0bzKPpVPst_StbsyD_DuLa |url-status=live |archive-url=https://web.archive.org/web/20200419193629/https://toshiba.semicon-storage.com/info/docget.jsp?did=10942&prodName=TMP86PM29BUG&usg=AOvVaw0bzKPpVPst_StbsyD_DuLa |archive-date=2020-04-19 |quote-page=61 |quote=[…] WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a don't care is read. […]}} (9+vi+190 pages)

{{cite web |title=Power-Up Don't Care logic option |publisher=Intel Corporation |date=2017 |work=Quartus Help |url=https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/mapIdTopics/mwh1465427440242.htm |access-date=2020-04-19 |url-status=live |archive-url=https://web.archive.org/web/20200419193454/https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/mapIdTopics/mwh1465427440242.htm |archive-date=2020-04-19}}

{{cite web |title=Power-up level of register is not specified – using unspecifed power-up level |publisher=Intel Corporation |date=2020 |work=Knowledge Base |url=https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd06172002_6171.html |access-date=2020-04-19 |url-status=live |archive-url=https://web.archive.org/web/20200419190611/https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd06172002_6171.html |archive-date=2020-04-19}}

{{cite journal |title=Karnaugh-Map Utilization in Boolean Analysis: The Case of War Termination |author-first1=Ali Muhammad Ali |author-last1=Rushdi |author-first2=Raid Mohammad Salih |author-last2=Badawi |date=January 2017 |series=Qualitative Comparative Analysis |journal=Journal of Engineering and Computer Sciences |location=Department of Electrical and Computer Engineering, King Abdulaziz University, Jeddah, Saudi Arabi / Qassim University |volume=10 |number=1 |id=Rabi'II 1438H |pages=53–88 [54–55, 57, 61–63] |url=https://www.researchgate.net/publication/316700735 |access-date=2021-02-17 |url-status=live |archive-url=https://web.archive.org/web/20210216234504/https://www.researchgate.net/publication/316700735_Karnaugh-Map_Utilization_in_Boolean_Analysis_The_Case_of_War_Termination |archive-date=2021-02-16}} [https://web.archive.org/web/20210217000340/https://www.researchgate.net/profile/Ali-Rushdi/publication/316700735_Karnaugh-Map_Utilization_in_Boolean_Analysis_The_Case_of_War_Termination/links/590db2eb0f7e9b2863a450dd/Karnaugh-Map-Utilization-in-Boolean-Analysis-The-Case-of-War-Termination.pdf]

{{Cite journal |title=On the Reduction of Superfluous States in a Sequential Machine |author-last=Ginsburg |author-first=Seymour |author-link=Seymour Ginsburg |journal=Journal of the ACM |issn= |date=1959-04-01 |volume=6 |issue=2 |doi=10.1145/320964.320983 |s2cid=10118067 |pages=259–282 |doi-access=free}}

{{cite conference |title=Don't care filling for power minimization in VLSI circuit testing |conference=2008 IEEE International Symposium on Circuits and Systems (ISCAS) |publisher=Institute of Electrical and Electronics Engineers |author-first1=Tapas Kr. |author-last1=Maiti |author-first2=Santanu |author-last2=Chattopadhyay |isbn=978-1-4244-1683-7 |edition=1 |issn=0271-4302 |eissn=2158-1525 |date=2008-05-18 |doi=10.1109/ISCAS.2008.4541998 |location=Seattle, Washington, USA |pages=2637–2640 |url=}}

{{cite book |chapter=Chapter 6. Logic Minimization for Low Power |title=Logic Synthesis for Low Power VLSI Designs |author-last1=Iman |author-first1=Sasan |author-last2=Pedram |author-first2=Massoud |author-link2=Massoud Pedram |location=University of Southern California, California, USA |date=1998 |orig-date=1997-11-30 |publisher=Kluwer Academic Publishers / Springer Science+Business Media, LLC |publication-place=Boston, Massachusetts, USA / New York, USA |edition=1 |doi=10.1007/978-1-4615-5453-0_6 |isbn=978-0-7923-8076-4 |lccn=97-042097 |pages=109–148 [110] |chapter-url=https://page-one.springer.com/pdf/preview/10.1007/978-1-4615-5453-0_6 |access-date=2024-07-26 |url-status=live |archive-url=https://web.archive.org/web/20240726155840/https://page-one.springer.com/pdf/preview/10.1007/978-1-4615-5453-0_6 |archive-date=2024-07-26}} (xv+236 pages) [https://books.google.com/books?id=NKTaBwAAQBAJ&pg=PA109]

{{cite book |title=Switching circuits for engineers |chapter=Chapter 6. Tabular method of simplification: Optional combinations |author-first=Mitchell Paul |author-last=Marcus |author-link=:d:Q90568170 |location=IBM, Endicott / Binghampton, New York, USA |date=c. 1970 |edition= |publisher=Edicion Revolucionaria, Instituto del Libro |publication-place=Habana, Cuba |id=19 No. 1002 |isbn= |pages=70–72 [71]}} (xiv+2+296+2 pages)

}}

• {{cite book |title=Testing Object-oriented Systems: Models, Patterns, and Tools |author-first1=Robert V. |author-last1=Binder |author-first2=Boris |author-link2=Boris Beizer |author-last2=Beizer |publisher=Addison-Wesley Professional |date=2000 |series=Addison-Wesley Object Technology Series |edition=illustrated reworked |isbn=978-0-20180938-1 |id={{ISBN|0-20180938-9}} |url=https://books.google.com/books?id=P3UkDhLHP4YC |access-date=2020-08-05}} (1191 pages)
• {{cite book |title=MCS-80 User's Manual (With Introduction to MCS-85) |chapter=Chapter 6. Microcomputer System Component Data Sheet - EPROMs and ROM: I. PROM and ROM Programming Instructions - B3. Non-Intellec Hex Paper Tape Format, C1. Intellec Hex Computer Punched Card Format, C2. PN Computer Punched Card Format |date=October 1977 |orig-date=1975 |publisher=Intel Corporation |id=98-153D |pages=6-77, 6-79 |url=https://archive.org/details/bitsavers_intelMCS80ualOct77_38961682/ |access-date=2020-02-27}} [https://archive.org/stream/bitsavers_intelMCS80ualOct77_38961682/98-153D__MCS-80_Users_Manual_Oct77_djvu.txt][https://archive.org/download/bitsavers_intelMCS80ualOct77_38961682/98-153D__MCS-80_Users_Manual_Oct77.pdf] (NB. Uses the term "don't care" data for address ranges in programmable memory chips which do not need to contain a particular value und thus can remain undefined in the programming instructions.)

{{DEFAULTSORT:Don't-Care (Logic)}}

Category:Logic