ETRAX CRIS
The ETRAX CRIS is a RISC ISA and series of CPUs designed and manufactured by Axis Communications for use in embedded systems since 1993.[http://developer.axis.com/old/products/history/etrax_history.html axis.com - Axis Chip Development History] {{webarchive |url=https://web.archive.org/web/20100530115423/http://developer.axis.com/old/products/history/etrax_history.html |date=May 30, 2010 }} The name is an acronym of the chip's features: Ethernet, Token Ring, AXis - Code Reduced Instruction Set. Token Ring support has been taken out from the latest chips as it has become obsolete.
Types of chips
The CGA-1 (Coax Gate Array) was the first microprocessor developed by Axis Communications. It contains IBM 3270 (coax) and IBM 5250 (Twinax) communications. The chip has a microcontroller and various I/O's such as serial and parallel. The CGA-1 chip was designed by Martin Gren and Staffan Göransson.{{cite web|url=http://www.axis.com/files/sales/axis_milestones_30years_1401_lo.pdf|title=30 years of milestones|website=Axis Communications}}Image:Elphel axis side.jpg Reconfigurable Network Camera based on ETRAX FS CPU and Xilinx Spartan 3e FPGA.]]Image:Acmesystems foxboard 4 16.jpg
= ETRAX =
- In 1993, Axis developed the ETRAX-1 Ethernet Controller, which has 10 Mbit/s Ethernet and Token Ring controllers.
- In 1995, Axis introduced the ETRAX-4 SoC which contains a Ethernet Controller, CPU, Memory Interface, SCSI controller, and parallel and serial I/O. {{Cite web |last=Zander |first=Per |title=Axis Communications - A World Of Intelligent Networks |url=https://www.eit.lth.se/fileadmin/eit/courses/eitn30/Forel/ii_etrax_13.pdf}}
- In 1997, Axis introduced the ETRAX 100 SoC which features a 10/100 Mbit/s Ethernet Controller, ATA controller, and Wide SCSI controller. The chip introduced on-chip unified instruction and data cache along with direct memory access.{{Cite web |date=1999-01-01 |title=ETRAX 100: technical specifications |url=http://www.axis.com/products/thinserver/etrax_data.html|language=en|archive-url=https://web.archive.org/web/20001017212431/http://www.axis.com/products/thinserver/etrax_data.html|archive-date=2000-10-17|url-status=dead}}
= ETRAX 100LX =
In 2000, Axis Introduced the ETRAX 100LX SoC which features a MMU, USB controller, and SDRAM interface. The CPU is capable of 100 MIPS. The chip is able to run the Linux kernel without modifications except for low-level support.The linux kernel source-code under /arch/cris contained the low-level CPU-specific additions required to make the Linux kernel able to run on the ETRAX/Cris CPUs. (See for example https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/cris?h=v4.13-rc4) The chip's maximum TDP is 0.35 Watts. As of Linux kernel 4.17, the architecture has been dropped due to being obsolete.{{Cite web |title=Linux-Kernel Archive: [PATCH 00/16] remove eight obsolete architectures |url=http://lkml.iu.edu/hypermail/linux/kernel/1803.1/06845.html}}
Specifications:
- 32-bit RISC CPU core
- 10/100 Mbit/s Ethernet controller
- 4 asynchronous serial ports
- 2 synchronous serial ports
- 2 USB ports
- 2 Parallel ports
- 4 ATA (IDE) ports
- 2 Narrow SCSI ports (or 1 Wide)
- Support for SDRAM, Flash, EEPROM, SRAM
=ETRAX 100LX MCM=
The ETRAX 100LX MCM is based on the ETRAX 100 LX. The chip has internal flash memory, SDRAM, and an Ethernet PHYceiver. The Chip can come with 2 MB flash and 8 MB SDRAM or 4 MB flash and 16 MB SDRAM.
= ETRAX FS =
Introduced in 2005 with full Linux 2.6 support, the chip features:
= ARTPEC =
{{Excerpt|Axis_Communications|Microprocessors}}
References
{{reflist}}
External links
- [http://developer.axis.com Home page]
- [http://developer.axis.com/wiki Developers wiki]