FPGA Mezzanine Card

The FMC specification defines:{{cite web|url=http://www.vita.com/fmc|title=FMC Marketing Alliance| accessdate=4 June 2012}}

• I/O mezzanine modules, which connect to carrier cards
• A high-speed connector family of connectors for I/O mezzanine modules
• Supporting up to 10 Gbit/s transmission with adaptively equalized I/O
• Supporting single ended and differential signaling up to 2 Gbit/s
• Numerous I/O available
• The electrical connectivity of the I/O mezzanine module high-speed connector
• Supporting a wide range of signaling standards
• System configurable I/O functionality
• FPGA intimacy
• The mechanical properties of the I/O mezzanine module
• Minimal size
• Scalable from low end to high performance applications
• Conduction and ruggedized support

The FMC specification has two defined sizes: single width (69 mm) and double width (139 mm). The depth of both is about 76.5 mm.{{cite web|url=https://fmchub.github.io/faq.html#fmc_form_factors| title=What form factors are specified by ANSI/VITA-57.1?|accessdate=24 July 2017}} The FMC mezzanine module uses a high-pin count 400 pin high-speed array connector. A mechanically compatible low pin count connector with 160 pins can also be used with any of the form factors in the standard.

FMC allows for two sizes of connector, Low Pin Count (LPC) and High Pin Count (HPC), each offering different (maximum) levels of connectivity,{{cite web|url=https://fmchub.github.io/appendix/VITA57_FMC_HPC_LPC_SIGNALS_AND_PINOUT.html|title=ANSI/VITA 57 FMC - Signals and Pinout|accessdate=24 July 2017}} analogous to how some PMC boards have a 32-bit interface while others have a 64-bit interface by using an additional connector. "The LPC connector provides 68 user-defined, single-ended signals or 34 user-defined, differential pairs. The HPC connector provides 160 user-defined, single-ended signals (or 80 user-defined, differential pairs), 10 serial transceiver pairs, and additional clocks. The HPC and LPC connectors use the same mechanical connector. The only difference is which signals are actually populated. Thus, cards with LPC connectors can be plugged into HPC sites, and if properly designed, HPC cards can offer a subset of functionality when plugged into an LPC site."{{Citation

| last = Seelam

| first = Raj

| title = I/O Design Flexibility with the FPGA Mezzanine Card (FMC) WP315

| publisher = Xilinx, Inc.

| date = August 19, 2009

| url = https://docs.amd.com/v/u/en-US/wp315

| access-date = }}

FMC provides a Geographical Address using two pins (GA1:GA0)

that are typically used by a mezzanine

device to determine which FMC connector on a carrier

it is attached to. For cards that have

only one FMC connector, the default

geographical address is 00.

Some FMC mezzanine cards may attach other devices

to the I2C bus and address them through a

system controller, using the geographical address

as a chip-select. This is not strictly in adherence

with the FMC specification.

• VPX
• Expansion slot
• CRUVI FPGA daughtercard standard with FMC option

{{Reflist}}

{{DEFAULTSORT:FMC - FPGA Mezzanine Card}}

Category:American National Standards Institute standards