ICE (FPGA)#iCE40 (40 nm)

{{Infobox company

| name = SiliconBlue Technologies Corporation

| logo = SiliconBlue Technologies (Post-Lattice) Logo.gif

| logo_caption = The logo used by SiliconBlue following their being acquired in 2011.

| type = Private

| industry = Integrated circuits

| products = FPGAs

| founded = {{start date|2005|04|12}}{{URL|http://kepler.sos.ca.gov|California Secretary of State Business Search}}, entity number C2632216.

| fate = Acquired by Lattice Semiconductor

| defunct = {{end date|2011|12|9}}

| founders = {{ubl|Kapil Shankar {{small|(CEO)}}|Jack Peng {{small|(CTO)}}|Andrew Chan {{small|(VP Engineering)}}|John Birkner {{small|(Product Definition)}}}}

| hq_location_city = Santa Clara, California

| hq_location_country = United States

| website = {{URL|https://web.archive.org/web/20120208003648/http://www.siliconbluetech.com/|www.siliconbluetech.com}} (archived copy from 2012)

}}

File:Sb stamp.jpg

The iCE brand was originally used by SiliconBlue Technologies Corporation, a former Santa Clara, California-based fabless designer of integrated circuits. SiliconBlue was a start-up founded in 2005 by former employees of Actel, AMD, Lattice, Monolithic Memories, and Xilinx.{{cite web | url=http://www.siliconbluetech.com/team.htm | title=SiliconBlue Team | publisher=SiliconBlue Technologies | date=2006 | access-date=13 May 2016 | archive-date=6 December 2006 | archive-url=https://web.archive.org/web/20061206215956/http://www.siliconbluetech.com/team.htm | url-status=usurped}} Most notable among the founders was John Birkner, one of the inventors of programmable array logic.{{cite web | url=http://www.computerhistory.org/siliconengine/pal-user-programmable-logic-devices-introduced/ | title=1978: PAL User-Programmable Logic Devices Introduced | publisher=Computer History Museum | work=The Silicon Engine - A Timeline of Semiconductors in Computers | access-date=13 May 2016 | archive-date=1 April 2016 | archive-url=https://web.archive.org/web/20160401034348/http://www.computerhistory.org/siliconengine/pal-user-programmable-logic-devices-introduced/ | url-status=live}}

In 2006, SiliconBlue was funded with $16 million in "Series A" capital,{{cite press release | url=http://www.businesswire.com/news/home/20081022005376/en/SiliconBlue-Secures-24-Million-Series-B-Funding | title=SiliconBlue Secures $24 Million in Series-B Funding | publisher=SiliconBlue Technologies | date=22 October 2008 | access-date=13 May 2016 | archive-date=13 May 2016 | archive-url=https://web.archive.org/web/20160513161404/http://www.businesswire.com/news/home/20081022005376/en/SiliconBlue-Secures-24-Million-Series-B-Funding | url-status=live}} and in June 2008 announced the iCE65 L series of devices. The devices were to be fabricated on TSMC's 65{{thinsp}}nm CMOS process node, which SiliconBlue claimed would provide reduced power consumption compared to contemporary FPGAs from other manufacturers. In October 2008, SiliconBlue raised a further $24 million in Series B capital.

In 2009, the first iCE65 L devices were shipped to customers. SiliconBlue also registered SiliconBlue Technologies (Hong Kong) Limited, which remains as a subsidiary of Lattice Semiconductor.{{URL|https://www.icris.cr.gov.hk/csci/cps_criteria.jsp|Company Particulars Search - ICRIS CSC Companies Registry}}, CR number 1330814.{{cite web | url=https://www.sec.gov/Archives/edgar/data/855658/000085565816000180/ex-211201510xk.htm | title=Exhibit 21.1 - Subsidiaries of the Registrant | publisher=US Securities and Exchange Commission | date=2 March 2016 | access-date=13 May 2016}}

In 2010, the lowest-end of the iCE65 P devices was announced by SiliconBlue. The devices were claimed to be as much as 30% faster than iCE65 L devices while maintaining similar power consumption.{{cite news | url=http://www.eetimes.com/document.asp?doc_id=1313688 | title=SiliconBlue unveils new series of FPGAs targeting mobile apps | work=EETimes | date=17 February 2010 | access-date=13 May 2016 | archive-date=13 May 2016 | archive-url=https://web.archive.org/web/20160513175945/http://www.eetimes.com/document.asp?doc_id=1313688 | url-status=live}} In the June of the same year, SiliconBlue closed a $15 million Series C funding round.{{cite press release | url=http://www.businesswire.com/news/home/20100607006486/en/SiliconBlue-Completes-15M-Series-Preferred-Stock-Financing | title=SiliconBlue Completes $15M Series C Preferred Stock Financing | publisher=BusinessWire | date=7 June 2010 | access-date=13 May 2016 | archive-date=13 May 2016 | archive-url=https://web.archive.org/web/20160513180330/http://www.businesswire.com/news/home/20100607006486/en/SiliconBlue-Completes-15M-Series-Preferred-Stock-Financing | url-status=live}}

In April 2011, SiliconBlue announced that it was to release new product families, code-named "Los Angeles" and "San Francisco," using a TSMC 40{{thinsp}}nm process node.{{cite news | url=http://www.eetimes.com/document.asp?doc_id=1270781 | title=SiliconBlue tips FPGA move to 40-nm | work=EETimes | date=5 April 2011 | access-date=13 May 2016 | author=Clarke, Peter | archive-date=13 May 2016 | archive-url=https://web.archive.org/web/20160513181135/http://www.eetimes.com/document.asp?doc_id=1270781 | url-status=live}} The production of devices on a 40{{thinsp}}nm process node was further confirmed in June 2011, when SiliconBlue received $18 million in Series D funding to bring 40{{thinsp}}nm devices to market.{{cite press release | url=http://www.businesswire.com/news/home/20110629005541/en/SiliconBlue-Raises-18-Million-Series-Funding | title=SiliconBlue Raises $18 Million in Series D Funding | publisher=BusinessWire | date=29 June 2011 | access-date=13 May 2016 | archive-date=7 May 2012 | archive-url=https://web.archive.org/web/20120507071631/http://www.businesswire.com/news/home/20110629005541/en/SiliconBlue-Raises-18-Million-Series-Funding | url-status=live}}{{cite news | url=https://techcrunch.com/2011/06/29/siliconblue-scores-18-million-in-series-d-funding/ | title=SiliconBlue Scores $18 Million in Series D Funding | work=TechCrunch | date=29 June 2011 | access-date=13 May 2016 | author=Wauters, Robin | archive-date=10 March 2016 | archive-url=https://web.archive.org/web/20160310073750/http://techcrunch.com/2011/06/29/siliconblue-scores-18-million-in-series-d-funding/ | url-status=live}} The iCE40 product family was officially released in July 2011.{{cite news | url=http://www.eetimes.com/document.asp?doc_id=1316702 | title=SiliconBlue launches 40nm mobileFPGA family (code name "Los Angeles") | work=EETimes | date=11 July 2011 | access-date=13 May 2016 | author=Maxfield, Clive | archive-date=13 May 2016 | archive-url=https://web.archive.org/web/20160513184640/http://www.eetimes.com/document.asp?doc_id=1316702 | url-status=live}}

On 9 December 2011, SiliconBlue Technologies was acquired by Lattice Semiconductor in a $63.2 million cash buyout. As part of this buyout, Lattice received the iCE brand, manufacturing capabilities with TSMC, and a licence for various patents from Kilopass Technologies, including for its XPM one-time programmable (OTP) memory technology.{{cite book | url=https://www.sec.gov/Archives/edgar/data/855658/000085565812000035/a201110-k12x31x2011.htm | title=Form 10-K - Lattice Semiconductor Corporation | publisher=US Securities and Exchange Commission | year=2012}}{{rp|15, 8, 11}}

In April 2012, Lattice announced that the iCE65 families would be discontinued. The iCE40 LP and HX device families entered volume production the following month. The iCE40 LP family won the Elektra Digital Semiconductor Product of the Year award for 2012.

In July 2014, the iCE40 Ultra family was announced.

In February 2015, Lattice launched the iCE40 UltraLite device family. The devices in this family are claimed to operate at 30% less power than those of unspecified competitors, and are claimed to be the world's smallest FPGAs, being available in 1.4×1.4{{thinsp}}mm packages. The family won the 2015 Elektra Digital Semiconductor Product of the Year award.

In December 2016, Lattice launched the iCE40 UltraPlus device family. UltraPlus devices provide additional memory, additional processing elements, and support for newer interfaces and protocols compared to previous iCE40 Ultra/UltraLite devices.

File:Lattice iCE40LP-HX1K arch.png

{{see also|FPGA#Technical design|FPGA#Architecture}}

iCE65 and iCE40 devices are constructed as an array of programmable logic blocks (PLBs), where a PLB is a block of eight logic cells. Each logic cell consists of a four-input lookup table (sometimes called a 4-LUT or LUT4) with the output connected to a D flip-flop (a 1-bit storage element). Within a PLB, each logic cell is connected to the following and preceding cell by carry logic, intended to improve the performance of constructs such as adders and subtractors. Interspersed with PLBs are blocks of RAM, each four kilobits in size. The number of RAM blocks varies depending on the device.{{rp|pages=. 2-1 to 2-3}}{{rp|pages=. 5–9}}

Compared to LUT6-based architectures (such as Xilinx 7-series devices and Altera Stratix devices), a LUT4-based device is unable to implement as-complex logic functions with the same number of logic cells. For example, a logic function with seven inputs could be implemented in eight LUT4s or two LUT6s.

iCE devices use volatile SRAM to store configuration data. As a result, the data must be loaded onto the device each time power is lost. All iCE devices support loading configuration data from a programmer, from an external flash memory chip, or, with the exception of iCE40 LM devices, from a so-called NVCM, or non-volatile configuration memory. The NVCM is a one-time-programmable (OTP) memory integrated into the FPGA to negate the need for an external memory chip. Lattice claims that using the NVCM can improve design security by making reverse engineering more difficult.{{cite book | title=Lattice TN1248 - iCE40 Programming and Configuration v2.8 | publisher=Lattice Semiconductor | year=2015}}

The I/O pins on iCE devices are separated into up to four banks. On some devices each bank has its own power-supply pin (labelled V_CCIO), allowing the logic-high voltage level of the I/O bank to be adjusted.{{rp|2–7}} Configurable I/O voltage levels are used by iCE devices to allow support for multiple interface standards with voltage levels between 1.8{{thinsp}}V and 3.3{{thinsp}}V, such as LVDS.{{rp|3-1}} iCE65 devices also listed being able to support SSTL through this method.{{rp|11}}

{{main|Hardware description language|Design flow (EDA)}}

iCE FPGAs, as with most FPGAs and CPLDs, are typically designed for using a hardware description language (HDL), which describes an electronic circuit. Lattice iCEcube2, the IDE provided by Lattice for developing on their FPGAs, supports the VHDL and Verilog languages, as well as the EDIF format.

The details of a specific FPGA's bitstream format (which defines how the internal elements of the FPGA are connected and interact with each other) are not usually published by FPGA vendors. This means that, generally, an engineer creating a design for an FPGA must use the tools provided by the FPGA's manufacturer.

In December 2015, at 32C3,{{cite web|url=https://events.ccc.de/congress/2015/Fahrplan/events/7139.html |title=Schedule 32. Chaos Communication Congress |publisher=Chaos Computer Club |access-date=8 April 2016 |url-status=unfit |archive-url=https://web.archive.org/web/20160108202522/https://events.ccc.de/congress/2015/Fahrplan/events/7139.html |archive-date=January 8, 2016 }} Project IceStorm, a toolchain consisting of Yosys (Verilog synthesis frontend), Arachne-pnr (place and route and bitstream generation), and icepack (plain text-to-binary bitstream conversion) tools was presented by Claire Wolf, one of the two developers (along with Mathias Lasser) of the toolchain.{{cite web|last1=Wolf|first1=Claire|last2=Lasser|first2=Matthias|title=Project IceStorm|url=http://bygone.clairexen.net/icestorm/|access-date=March 6, 2021|quote=In papers and reports, please refer to Project IceStorm as follows: Claire Wolf, Mathias Lasser. Project IceStorm.}} The toolchain is notable for being one of, if not the only, fully open-source toolchains for FPGA development. At the same December 2015 presentation, Wolf also demonstrated a RISC-V SoC design built using the open-source toolchain and running on an iCE40 HX8K device. As of March 2021, the toolchain supports iCE40 LP/HX 1K/4K/8K and UP devices.{{cite web|url=http://bygone.clairexen.net/icestorm/ |title=Project IceStorm |publisher=Claire Wolf |url-status=unfit |archive-url=https://web.archive.org/web/20210306021822/http://bygone.clairexen.net/icestorm/ |archive-date=March 6, 2021 }}

The iCE65 name was used by SiliconBlue Technologies for the devices it designed for a 65{{thinsp}}nm process node. Following the acquisition of SiliconBlue in 2011, the name was used by Lattice Semiconductor until the family was discontinued in April 2012.{{cite book | title=PCN# 08B-12: Notification of Intent to Discontinue the iCE65 Product Family | publisher=Lattice Semiconductor | year=2012}}

The iCE65 L series of devices was intended for low-power applications and handheld devices. The series was first announced in mid 2008,{{cite web|url=https://www.reuters.com/article/idUS123525+02-Jun-2008+BW20080602 |title=SiliconBlue Pioneers New FPGA Technology for Handheld, Ultra-Low Power Applications |publisher=SiliconBlue Technologies |date=2 June 2008 |access-date=9 April 2016 |url-status=dead |archive-url=https://web.archive.org/web/20160409075954/https://www.reuters.com/article/idUS123525%2B02-Jun-2008%2BBW20080602 |archive-date=9 April 2016 }} and first shipped to volume customers in early 2009.{{cite web|url=http://www.eetimes.com/document.asp?doc_id=1311490 |title=SiliconBlue announces volume production shipments of iCE65 ultra-low-power FPGAs |publisher=EETimes |date=9 February 2009 |access-date=6 April 2016 |url-status=unfit |archive-url=https://web.archive.org/web/20160406165932/http://www.eetimes.com/document.asp?doc_id=1311490 |archive-date=April 6, 2016 }}

Information about a larger device in the series, the iCE65L16, was listed on the SiliconBlue website in 2010,{{cite web|url=http://www.siliconbluetech.com/products/devices/pro_iCE65_L_Series_mobileFPGA.aspx |title=SiliconBlue Technologes: iCE65 L-Series |publisher=SiliconBlue Technologies |access-date=6 April 2016 |url-status=unfit |archive-url=https://web.archive.org/web/20100220211548/http://www.siliconbluetech.com/products/devices/pro_iCE65_L_Series_mobileFPGA.aspx |archive-date=February 20, 2010 }} but no mention is made in a 2012 revision of the L-series datasheet.{{cite book | title=iCE65™ Ultra Low-Power mobileFPGA™ Family Datasheet v2.42 | publisher=Lattice Semiconductor | year=2012}} It is unclear whether the device was ever produced commercially.

The iCE65 P-series devices were marketed as a higher-performance version of the L-series devices, intended for use in display, memory, and SERDES applications,{{cite book | title=The iCE65 mobileFPGA Family Product Table v1.1 | publisher=Lattice Semiconductor }} and were announced in early 2010.{{cite press release|url=https://www.reuters.com/article/idUS42638+15-Feb-2010+BW20100215 |title=SiliconBlue Enables Differentiated Mobile Broadband Products with New P-Series mobileFPGA Devices |publisher=Reuters |date=15 February 2010 |access-date=6 April 2016 |url-status=dead |archive-url=https://web.archive.org/web/20101117204221/https://www.reuters.com/article/idUS42638%2B15-Feb-2010%2BBW20100215 |archive-date=17 November 2010 }} Three devices were listed as being part of the series but only one device, the lowest-end iCE65P04, was fully specified. The latest datasheet for the family, published in 2011, lists the other two parts but does not give specifications.{{cite book | title=iCE65™ P-Series Ultra Low-Power mobileFPGA™ Family v1.31 | publisher=SiliconBlue Technologies | date=22 April 2011 }} Whether these other two devices were ever commercially produced is unclear.

{{clear}}

Lattice uses the iCE40 name for its iCE-branded devices produced on a 40{{thinsp}}nm process node. The company has also used the codename "Los Angeles" in press releases. The iCE40 family was launched in July 2011 with iCE40 LP and HX parts, and was updated in July 2014 with the iCE40 Ultra parts, in February 2015 with the iCE40 UltraLite parts, and in December 2016 with the iCE40 UltraPlus parts.

The iCE40 Ultra, UltraLite, and UltraPlus devices are intended for applications with especially low limits on available space and power, such as in wearable technology and smart watches.{{cite web|url=http://latticesemi.com/en/About/Newsroom/PressReleases/2015/20151201iCE40UltraWearable.aspx |title=Lattice Semiconductor Launches iCE40 Ultra™ Platform for Wearable Device Development |publisher=Lattice Semiconductor |date=1 December 2015 |access-date=5 April 2016 |url-status=unfit |archive-url=https://web.archive.org/web/20160331093934/http://latticesemi.com/en/About/Newsroom/PressReleases/2015/20151201iCE40UltraWearable.aspx |archive-date=March 31, 2016 }} They are offered in chip-scale, BGA, and QFN packages, with dimensions from 1.4×1.4{{thinsp}}mm to 7×7{{thinsp}}mm. All devices in family integrate one or two I²C hard cores, with Ultra and UltraPlus devices also including hard SPI bus cores and DSP blocks. UltraLite devices are claimed to operate at half the static current draw of Ultra devices (35{{thinsp}}μA compared to 71{{thinsp}}μA). Most devices in the family also include a PWM controller, intended to be used to drive IR or RGB LEDs.{{cite book | title=TN 1288 - iCE40 LED Driver Usage Guide | publisher=Lattice Semiconductor | year=2014}}{{rp|5}}

Lattice launched the Ultra family in mid 2014, and the UltraLite family in early 2015.{{cite web|url=http://latticesemi.com/en/About/Newsroom/PressReleases/2015/201502UltraLite.aspx |title=Lattice Semiconductor's New iCE40 UltraLite Device Enables OEMs to Accelerate Time-to-Market of Feature-Rich Mobile Devices |publisher=Lattice Semiconductor |date=3 February 2015 |access-date=5 April 2016 |url-status=unfit |archive-url=https://web.archive.org/web/20160331095525/http://latticesemi.com/en/About/Newsroom/PressReleases/2015/201502UltraLite.aspx |archive-date=March 31, 2016 }} In 2015, the UltraLite family won the Elektra Digital Semiconductor Product of the Year award.{{cite web|url=http://www.elektraawards.co.uk/elektraawards2016/2015-winners |title=2015 Winners :: Elektra Awards |publisher=Electronics Weekly |access-date=5 April 2016 |url-status=unfit |archive-url=https://web.archive.org/web/20160405194156/http://www.elektraawards.co.uk/elektraawards2016/2015-winners |archive-date=April 5, 2016 }}

In September 2016, the Apple iPhone 7 was released and made use of an iCE5LP4K device.{{cite web | url=http://www.chipworks.com/about-chipworks/overview/blog/apple-iphone-7-teardown | title=Apple iPhone 7 Teardown {{!}} Chipworks | publisher=Chipworks Inc. | date=15 September 2016 | access-date=17 September 2016 | archive-date=16 September 2016 | archive-url=https://web.archive.org/web/20160916230725/http://www.chipworks.com/about-chipworks/overview/blog/apple-iphone-7-teardown}}

In December 2016, Lattice launched the UltraPlus family intended for distributed processing and so-called "mobile heterogeneous computing." The devices include a 1{{nbsp}}Mbit (4×256{{nbsp}}kbit) single-port RAM (compare with dual-ported RAM), additional DSP processing elements, and support for additional interfaces, such as MIPI I3C, D-PHY, and Virtual GPIO.{{cite press release | url=http://www.latticesemi.com/About/Newsroom/PressReleases/2016/20161212NewiCE40UltraPlusDevices.aspx | title=New iCE40 UltraPlus Devices from Lattice Semiconductor Accelerate Customer Innovation in Smartphones and IoT Edge Devices | publisher=Lattice Semiconductor | date=12 December 2016 | access-date=28 May 2017 | archive-date=28 May 2017 | archive-url=https://web.archive.org/web/20170528152559/http://www.latticesemi.com/About/Newsroom/PressReleases/2016/20161212NewiCE40UltraPlusDevices.aspx | url-status=live}}{{cite news | url=http://www.eetimes.com/document.asp?doc_id=1331054 | title=Lattice introduces iCE40 UltraPlus high-performance low-power FPGAs | work=EETimes | date=22 December 2016 | access-date=28 May 2017 | author=Maxfield, Max | archive-date=30 January 2017 | archive-url=https://web.archive.org/web/20170130132650/http://www.eetimes.com/document.asp?doc_id=1331054 | url-status=live}}

{{clear}}

The iCE40 LP (low power) and LM (low power with hard IP) parts are intended for use in battery-powered devices as hardware accelerators and I/O port expanders, and for use in the same applications as iCE40 Ultra and UltraLite parts. Compared to the Ultra parts, LP and LM parts are available in a wider range of footprints, offer a greater number of resources (I/O pins, embedded RAM, and logic elements), but consume more power.{{cite web|url=http://latticesemi.com/Products/FPGAandCPLD/iCE40.aspx |title=iCE40 LP/HX/LM - Lattice Semiconductor |publisher=Lattice Semiconductor |access-date=6 April 2016 |url-status=unfit |archive-url=https://web.archive.org/web/20160325005933/http://latticesemi.com/Products/FPGAandCPLD/iCE40.aspx |archive-date=March 25, 2016 }}

LM devices integrate two I²C and two SPI hard cores, as well as two strobe generators. LP devices however lack hard IP cores, so logic cells must be spent to implement interface logic as "soft cores", which are less power-efficient and often slower than hard cores. Larger LP devices and all LM devices integrate one or two phase-locked loops.

The families were launched in mid 2011 and entered volume production in mid 2012.{{cite web|url=http://latticesemi.com/en/About/Newsroom/PressReleases/2012/201205ProductionReleaseOfiCE40LosAngeles.aspx |title=Lattice Announces Production Release Of iCE40 Los Angeles LP-Series And HX-Series mobileFPGA Device Families |publisher=Lattice Semiconductor |date=8 May 2012 |access-date=5 April 2016 |url-status=unfit |archive-url=https://web.archive.org/web/20160331092704/http://latticesemi.com/en/About/Newsroom/PressReleases/2012/201205ProductionReleaseOfiCE40LosAngeles.aspx |archive-date=March 31, 2016 }} They won the Elektra Digital Semiconductor Product of the Year award for 2012.{{cite web|url=http://www.elektraawards.co.uk/elektraawards2016/2012-winners |title=2012 Winners :: Elektra Awards |publisher=Electronics Weekly |access-date=6 April 2016 |url-status=unfit |archive-url=https://web.archive.org/web/20160406113851/http://www.elektraawards.co.uk/elektraawards2016/2012-winners |archive-date=April 6, 2016 }} In 2015, it was announced that ZTE would use LM devices to provide sensor hub and infrared remote control functionality in its Star 2 smartphone.{{cite web | url=http://uk.reuters.com/article/or-lattice-semiconductor-idUKnBw235326a+100+BSW20150623 | archive-url=https://web.archive.org/web/20160406114428/http://uk.reuters.com/article/or-lattice-semiconductor-idUKnBw235326a+100+BSW20150623 | url-status=dead | archive-date=6 April 2016 | title=ZTE Chooses Lattice Semiconductor for Feature Differentiation and Integration on Star 2 Smartphone | publisher=Reuters | date=23 June 2015 | access-date=6 April 2016}}

{{clear}}

The iCE40 HX devices are intended for high-performance applications. Compared to iCE40 LP and Ultra devices, they offer lower maximum propagation delay (7.30{{thinsp}}ns versus 9.00–9.36{{thinsp}}ns),{{cite book | title=DS1040 - iCE40 LP/HX Family Data Sheet v3.2 | publisher=Lattice Semiconductor | year=2015}}{{rp|3-13,3-15}} and more I/O pins. HX series devices consume significantly more static power and are available only in significantly larger footprints compared to Ultra and LP parts (7×7{{thinsp}}mm to 2×2{{thinsp}}cm). Similarly to the LP devices, HX parts do not provide hard IP cores, but do provide one or two phase-locked loops. Unlike other iCE40 devices, the HX parts are also available in QFP footprints.

The HX parts were launched in mid 2011 alongside the LP parts, and entered volume production in mid 2012.

• Digital logic

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{{Programmable Logic}}

Category:Field-programmable gate arrays