IMP-16

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+ IMP-16 registers

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style="width:10px; text-align:center;"| 15 | style="width:10px; text-align:center;"| 14 | style="width:10px; text-align:center;"| 13 | style="width:10px; text-align:center;"| 12 | style="width:10px; text-align:center;"| 11 | style="width:10px; text-align:center;"| 10 | style="width:10px; text-align:center;"| 09 | style="width:10px; text-align:center;"| 08 | style="width:10px; text-align:center;"| 07 | style="width:10px; text-align:center;"| 06 | style="width:10px; text-align:center;"| 05 | style="width:10px; text-align:center;"| 04 | style="width:10px; text-align:center;"| 03 | style="width:10px; text-align:center;"| 02 | style="width:10px; text-align:center;"| 01 | style="width:10px; text-align:center;"| 00 | style="width:auto;" | (bit position)

colspan="17" | Main registers

style="background:silver;color:black" | style="text-align:center;" colspan="16"| AC0 | style="width:auto; background:white; color:black;"| Accumulator

style="background:silver;color:black" | style="text-align:center;" colspan="16"| AC1 | style="width:auto; background:white; color:black;"| Accumulator

style="background:silver;color:black" | style="text-align:center;" colspan="16"| AC2 | style="width:auto; background:white; color:black;"| Acc/Base

style="background:silver;color:black" | style="text-align:center;" colspan="16"| AC3 | style="width:auto; background:white; color:black;"| Acc/Base

style="background:silver;color:black"

colspan="17" | Program counter

style="background:silver;color:black" | style="text-align:center;" colspan="16"| PC | style="background:white; color:black;"| Program Counter

colspan="17" | Stack

style="background:silver;color:black" | style="text-align:center;" colspan="16"| STK | style="background:white; color:black;"| (16 entries)

colspan="17" | Status Flags Register (FR)

style="background:silver;color:black" | style="text-align:center;"| L | style="text-align:center;"| OV | style="text-align:center;"| CY | style="text-align:center;"| GF | style="text-align:center;"| GF | style="text-align:center;"| GF | style="text-align:center;"| GF | style="text-align:center;"| GF | style="text-align:center;"| GF | style="text-align:center;"| GF | style="text-align:center;"| GF | style="text-align:center;"| GF | style="text-align:center;"| GF | style="text-align:center;"| GF | style="text-align:center;"| GF | style="text-align:center;"| GF | style="background:white; color:black" | Status

style="background:silver;color:black"

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File:NatSem IMP 16A 522J 1.jpg

The IMP-16, by National Semiconductor, was the first multi-chip 16-bit microprocessor, released in 1973. It consisted of five PMOS integrated circuits: four identical RALU chips, short for register and ALU, providing the data path, and one CROM, Control and ROM, providing control sequencing and microcode storage. The IMP-16 is a bit-slice processor; each RALU chip provides a 4-bit slice of the register and arithmetic that work in parallel to produce a 16-bit word length.[http://www.textfiles.com/bitsavers/pdf/national/imp/4200011A_User_of_RALU_Flags_Application_Note_Jun72.pdf "Use of RALU flags"]{{Dead link|date=January 2023 |bot=InternetArchiveBot |fix-attempted=yes }}.[http://www.textfiles.com/bitsavers/pdf/national/_dataSheets/RALU_dataSheet.pdf "IMP-00A/520 MOS/LSI register and arithmetic logic unit (RALU)"] {{Webarchive|url=https://web.archive.org/web/20160304101550/http://www.textfiles.com/bitsavers/pdf/national/_dataSheets/RALU_dataSheet.pdf |date=2016-03-04 }}. p. 1

Each RALU chip stores its own 4 bits of the program counter, several registers, the ALU, a 16-word LIFO stack, and status flags. There were four 16-bit accumulators, two of which could be used as index registers. The instruction set architecture was similar to that of the Data General Nova.{{cite web |title=IMP-16 Programming and Assembler Manual |url=http://www.bitsavers.org/components/national/imp/4200002B_IMP16_pgmg_Nov73.pdf |website=bitsavers |publisher=National Semiconductor |access-date=26 December 2021}} The chip set could be extended with the CROM chip (IMP-16A / 522D) that implemented 16-bit multiply and divide routines. The chipset was driven by a two-phase 715 kHz non-overlapping clock that had a +5 to -12 voltage swing. An integral part of the architecture was a 16-bit input mux that provided various condition bits from the ALUs such as zero, carry, overflow along with general purpose inputs.

The microprocessor was used in the IMP-16P microcomputer and Jacquard Systems' J100 but saw little other use.{{cite web | url=http://bitsavers.trailing-edge.com/components/national/imp/4200036A_IMP16P_Descr_1974.pdf | title=IMP-16C/200 IMP-16C/300 Microprocessors, IMP-16P Microcomputer Product Descriptions | date=1974}}{{cite journal |last1=Surdan |first1=Esther |title=Jacquard Systems Starts Small But Thinks Big |journal=Computerworld |date=November 21, 1977 |volume=XI |issue=47 |page=66 |url=https://books.google.com/books?id=3wLD-4p12toC&pg=PA66 |access-date=3 November 2022}} The IMP-16 was later superseded by the PACE and INS8900 single-chip 16-bit microprocessors, which had a similar architecture but were not binary compatible. It was also used in the Aston Martin Lagonda, thanks to National Semiconductor's chairman Peter Sprague being a major shareholder in Aston Martin at the time.https://sprague.com/peter-sprague/aston-martin/ {{Bare URL inline|date=August 2024}}