Icarus Verilog

{{Short description|Verilog simulation and synthesis tool}}

{{Infobox software

| name = Icarus Verilog

| logo = Icarus Verilog logo2.png

| logo size = 150px

| screenshot =

| developer = Stephen Williams

| released =

| latest release version = 12.0

| latest release date = {{Start date and age|2023|06|10|df=yes}}

| programming language = C++

| operating system = Linux, FreeBSD, OpenSolaris, AIX, Microsoft Windows, and {{nowrap|Mac OS X}}

| platform = Cross-platform

| language = English

| genre = Verilog Simulator

| license = GPL-2.0-or-later

| website = https://steveicarus.github.io/iverilog/

}}

Icarus Verilog is an implementation of the Verilog hardware description language compiler that generates netlists in the desired format (EDIF) and a simulator. It supports the 1995, 2001 and 2005 versions of the standard, portions of SystemVerilog, and some extensions.

Icarus Verilog is available for Linux, FreeBSD, OpenSolaris, AIX, Microsoft Windows, and {{nowrap|Mac OS X}}. Released under the GNU General Public License, Icarus Verilog is free software, an alternative to proprietary software like Cadence's Verilog-XL.

As of release 0.9, Icarus is composed of a Verilog compiler (including a Verilog preprocessor) with support for plug-in backends, and a virtual machine that simulates the design. To view waveforms, a program like GTKWave can be used. Release v10.0, besides general improvements and bug fixes, added preliminary support for VHDL, but the VHDL support has been abandoned as of 2018.