Intel 8008#INTERP

{{Use dmy dates|date=October 2018|cs1-dates=y}}

{{Short description|8-bit microprocessor}}

{{Infobox CPU

|name = Intel 8008

|image= KL_Intel_C8008-1.jpg

|caption = An Intel C8008-1 processor variant with purple ceramic, gold-plated metal lid and pins

|produced-start = April 1972

|produced-end = 1983{{cite web |title=The Life Cycle of a CPU |url=https://www.cpushack.com/life-cycle-of-cpu.html |website=www.cpushack.com}}

|slowest = 500 | slow-unit = kHz

|fastest = 800 | fast-unit = kHz

|size-from = 10 μm

|transistors = 3,500

|application = Computer terminals, calculators, bottling machines, 1970s ASEA industrial robots{{cite web |url=http://www02.abb.com/global/gad/gad02077.nsf/lupLongContent/4F792B65B20267C5C1256FBE00546364 |title=Thirty years in robotics – Robotics |date=2014-05-19 |archive-url=https://web.archive.org/web/20140319013015/http://www02.abb.com/global/gad/gad02077.nsf/lupLongContent/4F792B65B20267C5C1256FBE00546364 |access-date=2018-04-11 |archive-date=2014-03-19}} (IRB 6), simple computers, etc.

|manuf1 = Intel

|designfirm = Computer Terminal Corporation (CTC)

|arch = 8008

|pack1 = 18-pin dual in-line package

|predecessor =

|successor = Intel 8080

|data-width = 8 bits

|address-width = 14 bits

|sock1 = DIP18

|support status = Unsupported

|soldby=Intel}}

The Intel 8008 ("eight-thousand-eight" or "eighty-oh-eight") is an early 8-bit microprocessor capable of addressing 16 KB of memory, introduced in April 1972. The 8008 architecture was designed by Computer Terminal Corporation (CTC) and was implemented and manufactured by Intel. While the 8008 was originally designed for use in CTC's Datapoint 2200 programmable terminal, an agreement between CTC and Intel permitted Intel to market the chip to other customers after Seiko expressed an interest in using it for a calculator.

History

In order to address several issues with the Datapoint 3300, including excessive heat radiation, Computer Terminal Corporation (CTC) designed the architecture of the 3300's planned successor with a CPU as part of the internal circuitry re-implemented on a single chip. Looking for a company able to produce their chip design, CTC co-founder Austin O. "Gus" Roche turned to Intel, then primarily a vendor of memory chips.{{citation |author-first=Lamont |author-last=Wood |url=http://www.computerworld.com/article/2532590/computer-hardware/forgotten-pc-history--the-true-origins-of-the-personal-computer.html |title=Forgotten PC history: The true origins of the personal computer |journal=Computerworld |date=2008-04-08 |access-date=2014-12-02 |archive-date=2018-11-16 |archive-url=https://web.archive.org/web/20181116163842/https://www.computerworld.com/article/2532590/computer-hardware/forgotten-pc-history--the-true-origins-of-the-personal-computer.html |url-status=dead }} Roche met with Bob Noyce, who expressed concern with the concept; John Frassanito recalls that: {{quote|"Noyce said it was an intriguing idea, and that Intel could do it, but it would be a dumb move. He said that if you have a computer chip, you can only sell one chip per computer, while with memory, you can sell hundreds of chips per computer."}} Another major concern was that Intel's existing customer base purchased their memory chips for use with their own processor designs; if Intel introduced their own processor, they might be seen as a competitor, and their customers might look elsewhere for memory. Nevertheless, Noyce agreed to a US$50,000 development contract in early 1970 ({{Inflation|US|50000|1970|fmt=eq|r=-3}}). Texas Instruments (TI) was also brought in as a second supplier.{{fact|date=April 2024}}

In December 1969, Intel engineer Stan Mazor and a representative of CTC met to discuss options for the logic chipset to power a new CTC business terminal. Mazor, who had been working with Ted Hoff on the development of the Intel 4004, proposed that a one-chip programmable microprocessor might be less cumbersome and ultimately more cost effective than building a custom logic chipset. CTC agreed and development work began on the chip, which at the time was known as the 1201.{{cite web|url=https://www.intel.com/content/www/us/en/history/virtual-vault/articles/the-8008.html|title=The Intel 8008|work=Intel|access-date=December 15, 2024}}

TI was able to make samples of the 1201 based on Intel drawings, calling it the TMX 1795. These proved to be buggy and were rejected.{{cite web |last1=Shirriff |first1=Ken |title=The Texas Instruments TMX 1795: the (almost) first, forgotten microprocessor |url=https://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html |website=righto.com |access-date=6 March 2025}} Intel's own versions were delayed. CTC decided to re-implement the new version of the terminal using serial discrete TTL instead of waiting for a single-chip CPU. The new system was released as the Datapoint 2200 in the spring of 1970, with their first sale to General Mills on 25 May 1970. CTC paused development of the 1201 after the 2200 was released, as it was no longer needed. Later in early 1971, Seiko approached Intel, expressing an interest in using the 1201 in a scientific calculator, likely after seeing the success of the simpler 4004 used by Busicom in their business calculators. A small re-design followed, under the leadership of Federico Faggin, the designer of the 4004, now project leader of the 1201, expanding from a 16-pin to 18-pin design, and the new 1201 was delivered to CTC in late 1971.

By that point, CTC had once again moved on, this time to the parallel-architecture Datapoint 2200 II, which was faster than the 1201. CTC voted to end their involvement with the 1201, leaving the design's intellectual property to Intel instead of paying the $50,000 contract. Intel renamed it the 8008 and put it in their catalog in April 1972 priced at US$120 ({{Inflation|US|120|1972|fmt=eq}}). This renaming tried to ride off the success of the 4004 chip, by presenting the 8008 as simply a 4 to 8 port, but the 8008 is not based on the 4004.{{cite interview |author=Ken Shirriff |quote=First, the 4004 and the 8008 are entirely different chips. Marketing makes them sound like it's just a 4-bit and 8-bit version, but they're totally different. |url=https://oxide.computer/podcasts/on-the-metal/ken-shirriff/ |time=19:52 |date=2021-01-26 |interviewer1=Bryan Cantrill |interviewer2=Jessie Frazelle |interviewer3=Steve Tuck |work=Oxide Computing Podcast |title=On the Metal: Ken Shirriff }} The 8008 went on to be a commercially successful design. This was followed by the popular Intel 8080, and then the hugely successful Intel x86 family.

In the UK, a team at S. E. Laboratories Engineering (EMI) led by Tom Spink in 1972 built a microcomputer based on a pre-release sample of the 8008. Joe Hardman extended the chip with an external stack. This, among other things, gave it power-fail save and recovery. Joe also developed a direct screen printer. The operating system was written using a meta-assembler developed by L. Crawford and J. Parnell for a Digital Equipment Corporation PDP-11.Brunel University, 1974. Master of Technology dissertation, L. R. Crawford. The operating system was burnt into a PROM. It was interrupt-driven, queued, and based on a fixed page size for programs and data. An operational prototype was prepared for management, who decided not to continue with the project.{{fact|date=April 2024}}

The 8008 was the CPU for the very first commercial non-calculator personal computers (excluding the Datapoint 2200 itself): the US SCELBI kit and the pre-built French Micral N and Canadian MCM/70. It was also the controlling microprocessor for the first several models in Hewlett-Packard's 2640 family of computer terminals.{{fact|date=April 2024}}

{{anchor|INTERP}}In 1973, Intel offered an instruction set simulator for the 8008 named INTERP/8.{{cite book |title=MCS-8 Microcomputer Set - 8008 - 8 Bit Parallel Central Processor Unit - Users Manual |chapter=XI. Appendices III. MCS-8 Software Package - Simulator |date=1974 |orig-date=November 1973 |version=Revision 4, Second Printing |publisher=Intel Corporation |publication-place=Santa Clara, California, USA |id=MCS-056-0574/25K |pages=84–94 |url=https://en.wikichip.org/w/images/e/ec/MCS-8_User_Manual_%28Rev_4%29_%28Nov_1973%29.pdf |access-date=2023-11-25 |url-status=live |archive-url=https://web.archive.org/web/20231125221321/https://en.wikichip.org/w/images/e/ec/MCS-8_User_Manual_%28Rev_4%29_%28Nov_1973%29.pdf |archive-date=2023-11-25}} (132 pages) It was written in FORTRAN IV by Gary Kildall while he worked as a consultant for Intel.{{cite magazine |title=High-level language simplifies microcomputer programming |author-last=Kildall |author-first=Gary Arlen |author-link=Gary Arlen Kildall |website=Electronics |publisher=McGraw-Hill Education |date=1974-06-27 |pages=103–109 [108] |url=https://www.retrotechnology.com/dri/kildall_highlevel_1974.pdf |access-date=2021-11-14 |url-status=live |archive-url=https://web.archive.org/web/20211114174610/https://www.retrotechnology.com/dri/kildall_highlevel_1974.pdf |archive-date=2021-11-14}}{{cite web |title=8008 Simulator INTERP/8 |series=Microcomputer Software |publisher=Intel Corporation |publication-place=Santa Clara, California, USA |date=March 1975 |id=Product Code 98-118A. MCS-514-0375/27.5K |url=https://mark-ogden.uk/files/intel/publications/98-118A%208008%20Simulator%20Interp_8-Mar75.pdf |access-date=2023-11-25 |url-status=live |archive-url=https://web.archive.org/web/20231125173745/https://mark-ogden.uk/files/intel/publications/98-118A%208008%20Simulator%20Interp_8-Mar75.pdf |archive-date=2023-11-25}} (2 pages)

Design

File:Intel 8008 arch.svg

class="infobox" style="font-size:88%;width:29em;"

|+ Intel 8008 registers

style="text-align:center;"| 13

| style="text-align:center;"| 12

| style="text-align:center;"| 11

| style="text-align:center;"| 10

| style="text-align:center;"| 09

| style="text-align:center;"| 08

| style="text-align:center;"| 07

| style="text-align:center;"| 06

| style="text-align:center;"| 05

| style="text-align:center;"| 04

| style="text-align:center;"| 03

| style="text-align:center;"| 02

| style="text-align:center;"| 01

| style="text-align:center;"| 00

| (bit position)

colspan="15" | Main registers
style="background:silver;color:black"

| style="text-align:center; background:white" colspan="6"|  

| style="text-align:center;" colspan="8"| A

| style="width:auto; background:white; color:black;"| Accumulator

style="background:silver;color:black"

| style="text-align:center; background:white" colspan="6"|  

| style="text-align:center;" colspan="8"| B

| style="background:white; color:black;"| B register

style="background:silver;color:black"

| style="text-align:center; background:white" colspan="6"|  

| style="text-align:center;" colspan="8"| C

| style="background:white; color:black;"| C register

style="background:silver;color:black"

| style="text-align:center; background:white" colspan="6"|  

| style="text-align:center;" colspan="8"| D

| style="background:white; color:black;"| D register

style="background:silver;color:black"

| style="text-align:center; background:white" colspan="6"|  

| style="text-align:center;" colspan="8"| E

| style="background:white; color:black;"| E register

style="background:silver;color:black"

| style="text-align:center; background:white" colspan="6"|  

| style="text-align:center;" colspan="8"| H

| style="background:white; color:black;"| H register (indirect)

style="background:silver;color:black"

| style="text-align:center; background:white" colspan="6"|  

| style="text-align:center;" colspan="8"| L

| style="background:white; color:black;"| L register (indirect)

colspan="15" | Program counter
style="background:silver;color:black"

| style="text-align:center;" colspan="14"| PC

| style="background:white; color:black;"| Program Counter

colspan="15" | Push-down address call stack
style="background:silver;color:black"

| style="text-align:center;" colspan="14"| AS

| style="background:white; color:black;"| Call level 1

style="background:silver;color:black"

| style="text-align:center;" colspan="14"| AS

| style="background:white; color:black;"| Call level 2

style="background:silver;color:black"

| style="text-align:center;" colspan="14"| AS

| style="background:white; color:black;"| Call level 3

style="background:silver;color:black"

| style="text-align:center;" colspan="14"| AS

| style="background:white; color:black;"| Call level 4

style="background:silver;color:black"

| style="text-align:center;" colspan="14"| AS

| style="background:white; color:black;"| Call level 5

style="background:silver;color:black"

| style="text-align:center;" colspan="14"| AS

| style="background:white; color:black;"| Call level 6

style="background:silver;color:black"

| style="text-align:center;" colspan="14"| AS

| style="background:white; color:black;"| Call level 7

colspan="15" | Flags
style="background:silver;color:black"

| style="text-align:center; background:white" colspan="10" |  

| style="text-align:center;"| C

| style="text-align:center;"| P

| style="text-align:center;"| Z

| style="text-align:center;"| S

| style="background:white; color:black" | Flags{{cite book |title=8008 8 Bit Parallel Central Processor Unit |date=November 1973 |publisher=Intel |pages=14, 17 |edition=Rev 4, Second Printing |url=http://www.bitsavers.org/components/intel/MCS8/Intel_8008_8-Bit_Parallel_Central_Processing_Unit_Rev4_Nov73.pdf |access-date=30 April 2024}}{{efn|CPZS flags are presented as a group in this order during state 4 of the PCC cycle of the INP instruction.}}

The 8008 was implemented in 10 μm silicon-gate enhancement-mode PMOS logic. Initial versions could work at clock frequencies up to 0.5 MHz. This was later increased in the 8008-1 to a specified maximum of 0.8 MHz. Instructions take between 3 and 11 T-states, where each T-state is 2 clock cycles.{{cite web |title=MCS-8 Micro Computer Set Users Manual |publisher=Intel Corporation |date=1972 |url=http://dunfield.classiccmp.org/mod8/8008um.pdf |access-date=2010-12-04}}

Register–register loads and ALU operations take 5T (20 μs at 0.5 MHz), register–memory 8T (32 μs), while calls and jumps (when taken) take 11 T-states (44 μs).{{cite web |title=Intel 8008 Opcodes |url=http://www.pastraiser.com/cpu/i8008/i8008_opcodes.html |access-date=2010-12-04}}

The 8008 is a little slower in terms of instructions per second (36,000 to 80,000 at 0.8 MHz) than the 4-bit Intel 4004 and Intel 4040.{{cite web |title=Intel 8008 (i8008) microprocessor family |publisher=CPU World |date=2003–2010 |url=http://www.cpu-world.com/CPUs/8008/index.html |access-date=2010-12-04}} but since the 8008 processes data 8 bits at a time and can access significantly more RAM, in most applications it has a significant speed advantage over these processors. The 8008 has 3,500 transistors.{{cite web |url=http://www.intel.com/museum/archives/history_docs/Moore.htm |access-date=June 28, 2009 |url-status=dead |archive-url=https://web.archive.org/web/20090904175848/http://www.intel.com/museum/archives/history_docs/Moore.htm |archive-date=2009-09-04 |title=Gordon Moore and Moore's Law |author=Intel}}Intel (2012). [http://www.intel.com/content/dam/www/public/us/en/documents/corporate-information/history-intel-chips-timeline-poster.pdf "Intel Chips: timeline poster"].Intel (2008). [http://www.intel.com/pressroom/kits/quickreffam.htm "Microprocessor Quick Reference Guide"].

The chip, limited by its 18-pin DIP, has a single 8-bit bus working triple duty to transfer 8 data bits, 14 address bits, and two status bits. The small package requires about 30 TTL support chips to interface to memory.{{cite book |title=Oral History of Federico Faggin |date=22 September 2004 |publisher=Computer History Museum |page=82 |edition=X2941.2005 |url=http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf |access-date=2023-07-14}} For example, the 14-bit address, which can access "16 K × 8 bits of memory", needs to be latched by some of this logic into an external memory address register (MAR). The 8008 can access 8 input ports and 24 output ports.

For controller and CRT terminal use, this is an acceptable design, but it is rather cumbersome to use for most other tasks, at least compared to the next generations of microprocessors. A few early computer designs were based on it, but most would use the later and greatly improved Intel 8080 instead.{{citation needed|date=February 2017}}

= Related processor designs =

The subsequent 40-pin NMOS Intel 8080 expanded upon the 8008 registers and instruction set and implements a more efficient external bus interface (using the 22 additional pins). Despite a close architectural relationship, the 8080 was not made binary compatible with the 8008, so an 8008 program would not run on an 8080. However, as two different assembly syntaxes were used by Intel at the time, the 8080 could be used in an 8008 assembly-language backward-compatible fashion.

The Intel 8085 is an electrically modernized version of the 8080 that uses depletion-mode transistors and also added two new instructions.

The Intel 8086, the original x86 processor, is a non-strict extension of the 8080, so it loosely resembles the original Datapoint 2200 design as well. Almost every Datapoint 2200 and 8008 instruction has an equivalent not only in the instruction set of the 8080, 8085, and Z80, but also in the instruction set of modern x86 processors (although the instruction encodings are different).

=Features=

The 8008 architecture includes the following features:{{citation needed|date=February 2017}}

  • Seven 8-bit "scratchpad" registers: The main accumulator (A) and six other registers (B, C, D, E, H, and L).
  • 14-bit program counter (PC).
  • Seven-level push-down address call stack. Eight registers are actually used, with the top-most register being the PC.
  • Four condition code status flags: carry (C), even parity (P), zero (Z), and sign (S).
  • Indirect memory access using the H and L registers (HL) as a 14-bit data pointer (the upper two bits are ignored).

Instruction set

Instructions are all one to three bytes long, consisting of an initial opcode byte, followed by up to two bytes of operands which can be an immediate operand or a program address. Instructions operate on 8-bits only; there are no 16-bit operations. There is only one mechanism to address data memory: indirect addressing pointed to by a concatenation of the H and L registers, referenced as M. The 8008 does, however, support 14-bit program addresses. It has automatic CAL and RET instructions for multi-level subroutine calls and returns which can be conditionally executed, like jumps. Eight one-byte call instructions (RST) for subroutines exist at the fixed addresses 00h, 08h, 10h, ..., 38h. These are intended to be supplied by external hardware in order to invoke interrupt service routines, but can employed as fast calls. Direct copying may be made between any two registers or a register and memory. Eight math/logic functions are supported between the accumulator (A) and any register, memory, or an immediate value. Results are always deposited in A. Increments and decrements are supported for most registers but, curiously, not A. Register A does, however, support four different rotate instructions. All instructions are executed in 3 to 11 states. Each state requires two clocks.

class="wikitable" style="text-align:center"

!colspan=8| Opcode

colspan=2| Operandsrowspan=2| Mnemonicrowspan=2| Statesrowspan=2| Description
7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3
0000000Xalign=left| {{mono|HLT}}4align=left| Halt
00colspan=3|DDD000align=left| {{mono|INr}}5align=left| DDD ← DDD + 1 (except A and M)
00colspan=3|DDD001align=left| {{mono|DCr}}5align=left| DDD ← DDD - 1 (except A and M)
00000010align=left| {{mono|RLC}}5align=left| A1-7 ← A0-6; A0 ← Cy ← A7
00colspan=3|CC011align=left| {{mono|Rcc (RET conditional)}}3/5align=left| If cc true, P ← (stack)
00colspan=3|ALU100dataalign=left| {{mono|ADI ACI SUI SBI NDI XRI ORI CPI data}}8align=left| A ← A [ALU operation] data
00colspan=3|N101align=left| {{mono|RST n}}5align=left| (stack) ← P, P ← N x 8
00colspan=3|DDD110dataalign=left| {{mono|LrI data (Load r with immediate data)}}8/9align=left| DDD ← data
00XXX111align=left| {{mono|RET}}5align=left| P ← (stack)
00001010align=left| {{mono|RRC}}5align=left| A0-6 ← A1-7; A7 ← Cy ← A0
00010010align=left| {{mono|RAL}}5align=left| A1-7 ← A0-6; Cy ← A7; A0 ← Cy
00011010align=left| {{mono|RAR}}5align=left| A0-6 ← A1-7; Cy ← A0; A7 ← Cy
01colspan=3|CC000addloaddhialign=left| {{mono|Jcc add (JMP conditional)}}9/11align=left| If cc true, P ← add
0100colspan=3|port1align=left| {{mono|INP port}}8align=left| A ← Port (ports 0-7 only)
01colspan=5|port1align=left| {{mono|OUT port}}6align=left| Port ← A (ports 8-31 only)
01colspan=3|CC010addloaddhialign=left| {{mono|Ccc add (CAL conditional)}}9/11align=left| If cc true, (stack) ← P, P ← add
01XXX100addloaddhialign=left| {{mono|JMP add}}11align=left| P ← add
01XXX110addloaddhialign=left| {{mono|CAL add}}11align=left| (stack) ← P, P ← add
10colspan=3|ALUcolspan=3|SSSalign=left| {{mono|ADr ACr SUr SBr NDr XRr ORr CPr}}5/8align=left| A ← A [ALU operation] SSS
11colspan=3|DDDcolspan=3|SSSalign=left| {{mono|Lds (Load d with s)}}5/7/8align=left| DDD ← SSS
11111111align=left| {{mono|HLT}}4align=left| Halt
7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || States || Description
colspan=13|
colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU
colspan=5| A000colspan=2|FC, C falsealign=left| {{mono|ADr ADI (A ← A + arg)}}
colspan=5| B001colspan=2|FZ, Z falsealign=left| {{mono|ACr ACI (A ← A + arg + Cy)}}
colspan=5| C010colspan=2|FS, S falsealign=left| {{mono|SUr SUI (A ← A - arg)}}
colspan=5| D011colspan=2|FP, P oddalign=left| {{mono|SBr SBI (A ← A - arg - Cy)}}
colspan=5| E100colspan=2|TC, C truealign=left| {{mono|NDr NDI (A ← A ∧ arg)}}
colspan=5| H101colspan=2|TZ, Z truealign=left| {{mono|XRr XRI (A ← A ⊻ arg)}}
colspan=5| L110colspan=2|TS, S truealign=left| {{mono|ORr ORI (A ← A ∨ arg)}}
colspan=5| M111colspan=2|TP, P evenalign=left| {{mono|CPr CPI (A - arg)}}
colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU

=Code example 1=

File:Intel 8008 wafer.jpg

The following 8008 assembly source code is for a subroutine named MEMCPY that copies a block of data bytes of a given size from one location to another. Intel's 8008 assembler supported only + and - operators. This example borrows the 8080's assembler AND and SHR (shift right) operators to select the low and high bytes of a 14-bit address for placement into the 8 bit registers. A contemporaneous 8008 programmer was expected to calculate the numbers and type them in for the assembler.

001700 000

001701 000

001702 000

001703 000

001704 000

001705 000

002000 066 304

002002 056 003

002004 327

002005 060

002006 317

002007 302

002010 261

002011 053

002012 302

002013 024 001

002015 320

002016 301

002017 034 000

002021 310

002022 066 300

002024 056 003

002026 302

002027 207

002030 340

002031 060

002032 301

002033 217

002034 350

002035 364

002036 337

002037 066 302

002041 056 003

002043 302

002044 207

002045 340

002046 060

002047 301

002050 217

002051 350

002052 364

002053 373

002054 104 007 004

002057

|

; MEMCPY --

; Copy a block of memory from one location to another.

;

; Entry parameters

; SRC: 14-bit address of source data block

; DST: 14-bit address of target data block

; CNT: 14-bit count of bytes to copy

ORG 1700Q ;Data at 001700q

SRC DFB 0 ;SRC, low byte

DFB 0 ; high byte

DST DFB 0 ;DST, low byte

DFB 0 ; high byte

CNT DFB 0 ;CNT, low byte

DFB 0 ; high byte

ORG 2000Q ;Code at 002000q

MEMCPY LLI CNT AND 255 ;HL = addr(CNT)

LHI CNT SHR 8 ;(AND and SHR not supported)

LCM ;BC = CNT

INL

LBM

LOOP LAC ;If BC = 0,

ORB

RTZ ;Return

DECCNT LAC ;BC = BC - 1

SUI 1

LCA

LAB

SBI 0

LBA

GETSRC LLI SRC AND 255 ;HL = addr(SRC)

LHI SRC SHR 8

LAC ;HL = SRC + BC

ADM ;E = C + (HL)

LEA ;(lower sum)

INL ;point to upper SRC

LAB

ACM ;H = B + (HL) + CY

LHA ;(upper sum)

LLE ;L = E

LDM ;Load D from (HL)

GETDST LLI DST AND 255 ;HL = addr(DST)

LHI DST SHR 8

LAC ;HL = DST + BC

ADM ;ADD code same as above

LEA

INL

LAB

ACM

LHA

LLE

LMD ;Store D to (HL)

JMP LOOP ;Repeat the loop

END

In the code above, all values are given in octal. Locations {{code|SRC}}, {{code|DST}}, and {{code|CNT}} are 16-bit parameters for the subroutine named {{code|MEMCPY}}. In actuality, only 14 bits of the values are used, since the CPU has only a 14-bit addressable memory space. The values are stored in little-endian format, although this is an arbitrary choice, since the CPU is incapable of reading or writing more than a single byte into memory at a time. Since there is no instruction to load a register directly from a given memory address, the HL register pair must first be loaded with the address, and the target register can then be loaded from the M operand, which is an indirect load from the memory location in the HL register pair. The BC register pair is loaded with the {{code|CNT}} parameter value and decremented at the end of the loop until it becomes zero. Note that most of the instructions used occupy a single 8-bit opcode.

=Code example 2=

The following 8008 assembly source code is for a simplified subroutine named MEMCPY2 that copies a block of data bytes from one location to another. By reducing the byte counter to 8 bits, there is enough room to load all the subroutine parameters into the 8008's register file.

002000 307

002001 206 015 004

002004 370

002005 206 015 004

002010 021

002011 110 000 004

002014 007

002015 316

002016 364

002017 341

002020 315

002021 353

002022 331

002023 040

002024 013

002025 030

002026 007

002027

|

; MEMCPY2 --

; Copy a block of memory from one location to another

;

; Entry parameters in registers

; HL: 14-bit address of source data block

; DE: 14-bit address of target data block

; C: 8-bit count of bytes to copy. (1 to 256 bytes)

ORG 2000Q ;Code at 002000q

MEMCPY2 LAM ;Read source byte into A

CAL XCHGI ;Exchange HL<->DE and increment DE

LMA ;Save A to target byte

CAL XCHGI ;Exchange HL<->DE and increment DE

DCC ;Decrement byte counter

JFZ MEMCPY2 ;Continue for all bytes

RET

;Exchange DE and HL register pairs then increment DE as 16 bits

XCHGI LBL ;Exchange L and E

LLE

LEB

LBH ;Exchange H and D

LHD

LDB

INE ;Inc E, low byte of DE

RFZ ;Return if no carry

IND ;Otherwise inc high byte D

RET

END

Interrupts

File:JB.SIM8-01.jpg

Interrupts on the 8008 are only partially implemented. After the INT line is asserted, the 8008 acknowledges the interrupt by outputting a state code of S0,S1,S2 = 011 at T1I time. At the subsequent instruction fetch cycle, an instruction is "jammed" (Intel's word) by external hardware on the bus. Typically this is a one-byte RST instruction.

At this point, there is a problem. The 8008 has no provision to save its architectural state. The 8008 can only write to memory via an address in the HL register pair. When interrupted, there is no mechanism to save HL so there is no way to save the other registers and flags via HL. Because of this, some sort of external memory device such as a hardware stack or a pair of read/write registers must be attached to the 8008 via the I/O ports to help save the state of the 8008.{{cite journal |last1=Chamberklin |first1=Hal |title="Add a Stack to your 8008 |journal=Byte |date=October 1975 |volume=0 |issue=2 |pages=52–56 |url=https://archive.org/details/byte-magazine-1975-10/page/n53/mode/2up |access-date=5 October 2024}}

Designers

  • CTC (Instruction set and architecture): Victor Poor and Harry Pyle.
  • Intel (Implementation in silicon):
  • Ted Hoff and Stan Mazor proposed a single-chip implementation of the CTC architecture, using RAM-register memory rather than shift-register memory, and also added a few instructions and interrupt facility. The 8008 (originally called 1201) chip design started before the 4004 development. Hoff and Mazor, however, could not and did not develop a "silicon design" because they were neither chip designers nor process developers, and furthermore the necessary bootstrap load silicon-gate-based design methodology and circuits, under development by Federico Faggin for the 4004, were not yet available.{{cite journal |author-last1=Faggin |author-first1=Federico |author-link1=Federico Faggin |author-last2=Hoff, Jr. |author-first2=Marcian E. |author-link2=Marcian Hoff |author-last3=Mazor |author-first3=Stanley |author-link3=Stanley Mazor |author-last4=Shima |author-first4=Masatoshi |author-link4=Masatoshi Shima |title=The History of the 4004 |journal=IEEE Micro |volume=16 |issue=6 |pages=10–19 |publisher=IEEE Computer Society |location=Los Alamitos, USA |date=December 1996 |issn=0272-1732 |doi=10.1109/40.546561}}
  • Federico Faggin, having finished the design of the 4004, became leader of the project from January 1971 until its successful completion in April 1972, after it had been suspended – for lack of progress – for about seven months.
  • Hal Feeney, project engineer, did the detailed logic design, circuit design, and physical layout under Faggin's supervision, employing the same design methodology that Faggin had originally developed for the Intel 4004 microprocessor, and utilizing the basic circuits he had developed for the 4004. A combined "HF" logo was etched onto the chip about halfway between the D5 and D6 bonding pads.

Second sources

image:KL MME U808.jpg|VEB Mikroelektronik "Karl Marx" Erfurt (MME) U808 (GDR)

image:KL MF8008.jpg|MicroSystems International (MIL) MF8008

image:Siemens SAB8008 1C 1.jpg|Siemens SAB8008

See also

Notes

{{Notelist}}

References

{{Reflist|30em}}