Intel 8008#INTERP

In order to address several issues with the Datapoint 3300, including excessive heat radiation, Computer Terminal Corporation (CTC) designed the architecture of the 3300's planned successor with a CPU as part of the internal circuitry re-implemented on a single chip. Looking for a company able to produce their chip design, CTC co-founder Austin O. "Gus" Roche turned to Intel, then primarily a vendor of memory chips.{{citation |author-first=Lamont |author-last=Wood |url=http://www.computerworld.com/article/2532590/computer-hardware/forgotten-pc-history--the-true-origins-of-the-personal-computer.html |title=Forgotten PC history: The true origins of the personal computer |journal=Computerworld |date=2008-04-08 |access-date=2014-12-02 |archive-date=2018-11-16 |archive-url=https://web.archive.org/web/20181116163842/https://www.computerworld.com/article/2532590/computer-hardware/forgotten-pc-history--the-true-origins-of-the-personal-computer.html |url-status=dead }} Roche met with Bob Noyce, who expressed concern with the concept; John Frassanito recalls that: {{quote|"Noyce said it was an intriguing idea, and that Intel could do it, but it would be a dumb move. He said that if you have a computer chip, you can only sell one chip per computer, while with memory, you can sell hundreds of chips per computer."}} Another major concern was that Intel's existing customer base purchased their memory chips for use with their own processor designs; if Intel introduced their own processor, they might be seen as a competitor, and their customers might look elsewhere for memory. Nevertheless, Noyce agreed to a US$50,000 development contract in early 1970 ({{Inflation|US|50000|1970|fmt=eq|r=-3}}). Texas Instruments (TI) was also brought in as a second supplier.{{fact|date=April 2024}}

In December 1969, Intel engineer Stan Mazor and a representative of CTC met to discuss options for the logic chipset to power a new CTC business terminal. Mazor, who had been working with Ted Hoff on the development of the Intel 4004, proposed that a one-chip programmable microprocessor might be less cumbersome and ultimately more cost effective than building a custom logic chipset. CTC agreed and development work began on the chip, which at the time was known as the 1201.{{cite web|url=https://www.intel.com/content/www/us/en/history/virtual-vault/articles/the-8008.html|title=The Intel 8008|work=Intel|access-date=December 15, 2024}}

TI was able to make samples of the 1201 based on Intel drawings, calling it the TMX 1795. These proved to be buggy and were rejected.{{cite web |last1=Shirriff |first1=Ken |title=The Texas Instruments TMX 1795: the (almost) first, forgotten microprocessor |url=https://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html |website=righto.com |access-date=6 March 2025}} Intel's own versions were delayed. CTC decided to re-implement the new version of the terminal using serial discrete TTL instead of waiting for a single-chip CPU. The new system was released as the Datapoint 2200 in the spring of 1970, with their first sale to General Mills on 25 May 1970. CTC paused development of the 1201 after the 2200 was released, as it was no longer needed. Later in early 1971, Seiko approached Intel, expressing an interest in using the 1201 in a scientific calculator, likely after seeing the success of the simpler 4004 used by Busicom in their business calculators. A small re-design followed, under the leadership of Federico Faggin, the designer of the 4004, now project leader of the 1201, expanding from a 16-pin to 18-pin design, and the new 1201 was delivered to CTC in late 1971.

By that point, CTC had once again moved on, this time to the parallel-architecture Datapoint 2200 II, which was faster than the 1201. CTC voted to end their involvement with the 1201, leaving the design's intellectual property to Intel instead of paying the $50,000 contract. Intel renamed it the 8008 and put it in their catalog in April 1972 priced at US$120 ({{Inflation|US|120|1972|fmt=eq}}). This renaming tried to ride off the success of the 4004 chip, by presenting the 8008 as simply a 4 to 8 port, but the 8008 is not based on the 4004.{{cite interview |author=Ken Shirriff |quote=First, the 4004 and the 8008 are entirely different chips. Marketing makes them sound like it's just a 4-bit and 8-bit version, but they're totally different. |url=https://oxide.computer/podcasts/on-the-metal/ken-shirriff/ |time=19:52 |date=2021-01-26 |interviewer1=Bryan Cantrill |interviewer2=Jessie Frazelle |interviewer3=Steve Tuck |work=Oxide Computing Podcast |title=On the Metal: Ken Shirriff }} The 8008 went on to be a commercially successful design. This was followed by the popular Intel 8080, and then the hugely successful Intel x86 family.

In the UK, a team at S. E. Laboratories Engineering (EMI) led by Tom Spink in 1972 built a microcomputer based on a pre-release sample of the 8008. Joe Hardman extended the chip with an external stack. This, among other things, gave it power-fail save and recovery. Joe also developed a direct screen printer. The operating system was written using a meta-assembler developed by L. Crawford and J. Parnell for a Digital Equipment Corporation PDP-11.Brunel University, 1974. Master of Technology dissertation, L. R. Crawford. The operating system was burnt into a PROM. It was interrupt-driven, queued, and based on a fixed page size for programs and data. An operational prototype was prepared for management, who decided not to continue with the project.{{fact|date=April 2024}}

The 8008 was the CPU for the very first commercial non-calculator personal computers (excluding the Datapoint 2200 itself): the US SCELBI kit and the pre-built French Micral N and Canadian MCM/70. It was also the controlling microprocessor for the first several models in Hewlett-Packard's 2640 family of computer terminals.{{fact|date=April 2024}}

{{anchor|INTERP}}In 1973, Intel offered an instruction set simulator for the 8008 named INTERP/8.{{cite book |title=MCS-8 Microcomputer Set - 8008 - 8 Bit Parallel Central Processor Unit - Users Manual |chapter=XI. Appendices III. MCS-8 Software Package - Simulator |date=1974 |orig-date=November 1973 |version=Revision 4, Second Printing |publisher=Intel Corporation |publication-place=Santa Clara, California, USA |id=MCS-056-0574/25K |pages=84–94 |url=https://en.wikichip.org/w/images/e/ec/MCS-8_User_Manual_%28Rev_4%29_%28Nov_1973%29.pdf |access-date=2023-11-25 |url-status=live |archive-url=https://web.archive.org/web/20231125221321/https://en.wikichip.org/w/images/e/ec/MCS-8_User_Manual_%28Rev_4%29_%28Nov_1973%29.pdf |archive-date=2023-11-25}} (132 pages) It was written in FORTRAN IV by Gary Kildall while he worked as a consultant for Intel.{{cite magazine |title=High-level language simplifies microcomputer programming |author-last=Kildall |author-first=Gary Arlen |author-link=Gary Arlen Kildall |website=Electronics |publisher=McGraw-Hill Education |date=1974-06-27 |pages=103–109 [108] |url=https://www.retrotechnology.com/dri/kildall_highlevel_1974.pdf |access-date=2021-11-14 |url-status=live |archive-url=https://web.archive.org/web/20211114174610/https://www.retrotechnology.com/dri/kildall_highlevel_1974.pdf |archive-date=2021-11-14}}{{cite web |title=8008 Simulator INTERP/8 |series=Microcomputer Software |publisher=Intel Corporation |publication-place=Santa Clara, California, USA |date=March 1975 |id=Product Code 98-118A. MCS-514-0375/27.5K |url=https://mark-ogden.uk/files/intel/publications/98-118A%208008%20Simulator%20Interp_8-Mar75.pdf |access-date=2023-11-25 |url-status=live |archive-url=https://web.archive.org/web/20231125173745/https://mark-ogden.uk/files/intel/publications/98-118A%208008%20Simulator%20Interp_8-Mar75.pdf |archive-date=2023-11-25}} (2 pages)

File:Intel 8008 arch.svg

The 8008 was implemented in 10 μm silicon-gate enhancement-mode PMOS logic. Initial versions could work at clock frequencies up to 0.5 MHz. This was later increased in the 8008-1 to a specified maximum of 0.8 MHz. Instructions take between 3 and 11 T-states, where each T-state is 2 clock cycles.{{cite web |title=MCS-8 Micro Computer Set Users Manual |publisher=Intel Corporation |date=1972 |url=http://dunfield.classiccmp.org/mod8/8008um.pdf |access-date=2010-12-04}}

Register–register loads and ALU operations take 5T (20 μs at 0.5 MHz), register–memory 8T (32 μs), while calls and jumps (when taken) take 11 T-states (44 μs).{{cite web |title=Intel 8008 Opcodes |url=http://www.pastraiser.com/cpu/i8008/i8008_opcodes.html |access-date=2010-12-04}}

The 8008 is a little slower in terms of instructions per second (36,000 to 80,000 at 0.8 MHz) than the 4-bit Intel 4004 and Intel 4040.{{cite web |title=Intel 8008 (i8008) microprocessor family |publisher=CPU World |date=2003–2010 |url=http://www.cpu-world.com/CPUs/8008/index.html |access-date=2010-12-04}} but since the 8008 processes data 8 bits at a time and can access significantly more RAM, in most applications it has a significant speed advantage over these processors. The 8008 has 3,500 transistors.{{cite web |url=http://www.intel.com/museum/archives/history_docs/Moore.htm |access-date=June 28, 2009 |url-status=dead |archive-url=https://web.archive.org/web/20090904175848/http://www.intel.com/museum/archives/history_docs/Moore.htm |archive-date=2009-09-04 |title=Gordon Moore and Moore's Law |author=Intel}}Intel (2012). [http://www.intel.com/content/dam/www/public/us/en/documents/corporate-information/history-intel-chips-timeline-poster.pdf "Intel Chips: timeline poster"].Intel (2008). [http://www.intel.com/pressroom/kits/quickreffam.htm "Microprocessor Quick Reference Guide"].

The chip, limited by its 18-pin DIP, has a single 8-bit bus working triple duty to transfer 8 data bits, 14 address bits, and two status bits. The small package requires about 30 TTL support chips to interface to memory.{{cite book |title=Oral History of Federico Faggin |date=22 September 2004 |publisher=Computer History Museum |page=82 |edition=X2941.2005 |url=http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf |access-date=2023-07-14}} For example, the 14-bit address, which can access "16 K × 8 bits of memory", needs to be latched by some of this logic into an external memory address register (MAR). The 8008 can access 8 input ports and 24 output ports.

For controller and CRT terminal use, this is an acceptable design, but it is rather cumbersome to use for most other tasks, at least compared to the next generations of microprocessors. A few early computer designs were based on it, but most would use the later and greatly improved Intel 8080 instead.{{citation needed|date=February 2017}}

The subsequent 40-pin NMOS Intel 8080 expanded upon the 8008 registers and instruction set and implements a more efficient external bus interface (using the 22 additional pins). Despite a close architectural relationship, the 8080 was not made binary compatible with the 8008, so an 8008 program would not run on an 8080. However, as two different assembly syntaxes were used by Intel at the time, the 8080 could be used in an 8008 assembly-language backward-compatible fashion.

The Intel 8085 is an electrically modernized version of the 8080 that uses depletion-mode transistors and also added two new instructions.

The Intel 8086, the original x86 processor, is a non-strict extension of the 8080, so it loosely resembles the original Datapoint 2200 design as well. Almost every Datapoint 2200 and 8008 instruction has an equivalent not only in the instruction set of the 8080, 8085, and Z80, but also in the instruction set of modern x86 processors (although the instruction encodings are different).

The 8008 architecture includes the following features:{{citation needed|date=February 2017}}

• Seven 8-bit "scratchpad" registers: The main accumulator (A) and six other registers (B, C, D, E, H, and L).
• 14-bit program counter (PC).
• Seven-level push-down address call stack. Eight registers are actually used, with the top-most register being the PC.
• Four condition code status flags: carry (C), even parity (P), zero (Z), and sign (S).
• Indirect memory access using the H and L registers (HL) as a 14-bit data pointer (the upper two bits are ignored).

Instructions are all one to three bytes long, consisting of an initial opcode byte, followed by up to two bytes of operands which can be an immediate operand or a program address. Instructions operate on 8-bits only; there are no 16-bit operations. There is only one mechanism to address data memory: indirect addressing pointed to by a concatenation of the H and L registers, referenced as M. The 8008 does, however, support 14-bit program addresses. It has automatic CAL and RET instructions for multi-level subroutine calls and returns which can be conditionally executed, like jumps. Eight one-byte call instructions (RST) for subroutines exist at the fixed addresses 00h, 08h, 10h, ..., 38h. These are intended to be supplied by external hardware in order to invoke interrupt service routines, but can employed as fast calls. Direct copying may be made between any two registers or a register and memory. Eight math/logic functions are supported between the accumulator (A) and any register, memory, or an immediate value. Results are always deposited in A. Increments and decrements are supported for most registers but, curiously, not A. Register A does, however, support four different rotate instructions. All instructions are executed in 3 to 11 states. Each state requires two clocks.

File:Intel 8008 wafer.jpg

The following 8008 assembly source code is for a subroutine named MEMCPY that copies a block of data bytes of a given size from one location to another. Intel's 8008 assembler supported only + and - operators. This example borrows the 8080's assembler AND and SHR (shift right) operators to select the low and high bytes of a 14-bit address for placement into the 8 bit registers. A contemporaneous 8008 programmer was expected to calculate the numbers and type them in for the assembler.

001700  000
001701  000
001702  000
001703  000
001704  000
001705  000
002000  066 304
002002  056 003
002004  327
002005  060
002006  317
002007  302
002010  261
002011  053
002012  302
002013  024 001
002015  320
002016  301
002017  034 000
002021  310
002022  066 300
002024  056 003
002026  302
002027  207
002030  340
002031  060
002032  301
002033  217
002034  350
002035  364
002036  337
002037  066 302
002041  056 003
002043  302
002044  207
002045  340
002046  060
002047  301
002050  217
002051  350
002052  364
002053  373
002054  104 007 004
002057

In the code above, all values are given in octal. Locations {{code|SRC}}, {{code|DST}}, and {{code|CNT}} are 16-bit parameters for the subroutine named {{code|MEMCPY}}. In actuality, only 14 bits of the values are used, since the CPU has only a 14-bit addressable memory space. The values are stored in little-endian format, although this is an arbitrary choice, since the CPU is incapable of reading or writing more than a single byte into memory at a time. Since there is no instruction to load a register directly from a given memory address, the HL register pair must first be loaded with the address, and the target register can then be loaded from the M operand, which is an indirect load from the memory location in the HL register pair. The BC register pair is loaded with the {{code|CNT}} parameter value and decremented at the end of the loop until it becomes zero. Note that most of the instructions used occupy a single 8-bit opcode.

The following 8008 assembly source code is for a simplified subroutine named MEMCPY2 that copies a block of data bytes from one location to another. By reducing the byte counter to 8 bits, there is enough room to load all the subroutine parameters into the 8008's register file.

002000  307
002001  206 015 004
002004  370
002005  206 015 004
002010  021
002011  110 000 004
002014  007
002015  316
002016  364
002017  341
002020  315
002021  353
002022  331
002023  040
002024  013
002025  030
002026  007
002027

File:JB.SIM8-01.jpg

Interrupts on the 8008 are only partially implemented. After the INT line is asserted, the 8008 acknowledges the interrupt by outputting a state code of S0,S1,S2 = 011 at T1I time. At the subsequent instruction fetch cycle, an instruction is "jammed" (Intel's word) by external hardware on the bus. Typically this is a one-byte RST instruction.

At this point, there is a problem. The 8008 has no provision to save its architectural state. The 8008 can only write to memory via an address in the HL register pair. When interrupted, there is no mechanism to save HL so there is no way to save the other registers and flags via HL. Because of this, some sort of external memory device such as a hardware stack or a pair of read/write registers must be attached to the 8008 via the I/O ports to help save the state of the 8008.{{cite journal |last1=Chamberklin |first1=Hal |title="Add a Stack to your 8008 |journal=Byte |date=October 1975 |volume=0 |issue=2 |pages=52–56 |url=https://archive.org/details/byte-magazine-1975-10/page/n53/mode/2up |access-date=5 October 2024}}

• CTC (Instruction set and architecture): Victor Poor and Harry Pyle.
• Intel (Implementation in silicon):
• Ted Hoff and Stan Mazor proposed a single-chip implementation of the CTC architecture, using RAM-register memory rather than shift-register memory, and also added a few instructions and interrupt facility. The 8008 (originally called 1201) chip design started before the 4004 development. Hoff and Mazor, however, could not and did not develop a "silicon design" because they were neither chip designers nor process developers, and furthermore the necessary bootstrap load silicon-gate-based design methodology and circuits, under development by Federico Faggin for the 4004, were not yet available.{{cite journal |author-last1=Faggin |author-first1=Federico |author-link1=Federico Faggin |author-last2=Hoff, Jr. |author-first2=Marcian E. |author-link2=Marcian Hoff |author-last3=Mazor |author-first3=Stanley |author-link3=Stanley Mazor |author-last4=Shima |author-first4=Masatoshi |author-link4=Masatoshi Shima |title=The History of the 4004 |journal=IEEE Micro |volume=16 |issue=6 |pages=10–19 |publisher=IEEE Computer Society |location=Los Alamitos, USA |date=December 1996 |issn=0272-1732 |doi=10.1109/40.546561}}
• Federico Faggin, having finished the design of the 4004, became leader of the project from January 1971 until its successful completion in April 1972, after it had been suspended – for lack of progress – for about seven months.
• Hal Feeney, project engineer, did the detailed logic design, circuit design, and physical layout under Faggin's supervision, employing the same design methodology that Faggin had originally developed for the Intel 4004 microprocessor, and utilizing the basic circuits he had developed for the 4004. A combined "HF" logo was etched onto the chip about halfway between the D5 and D6 bonding pads.

image:KL MME U808.jpg|VEB Mikroelektronik "Karl Marx" Erfurt (MME) U808 (GDR)

image:KL MF8008.jpg|MicroSystems International (MIL) MF8008

image:Siemens SAB8008 1C 1.jpg|Siemens SAB8008

• Intel Intellec 8
• Mark-8 and SCELBI, 8008-based computer kits
• MCM/70 and Micral, pioneering microcomputers
• PL/M, the first programming language targeting a microprocessor, the Intel 8008, developed by Gary Kildall

{{Notelist}}

{{Reflist|30em}}

• [http://dunfield.classiccmp.org/mod8/8008um.pdf MCS-8 User Manual] with 8008 data sheet (1972)
• {{cite news |url=http://www.computerworld.com/article/2532590/computer-hardware/forgotten-pc-history--the-true-origins-of-the-personal-computer.html |newspaper=Computer World |author-first=Lamont |author-last=Wood |date=2008-08-08 |title=Forgotten PC history: The true origins of the personal computer |access-date=2014-12-02 |archive-date=2018-11-16 |archive-url=https://web.archive.org/web/20181116163842/https://www.computerworld.com/article/2532590/computer-hardware/forgotten-pc-history--the-true-origins-of-the-personal-computer.html |url-status=dead }}
• [http://petsd.net/8008.php The Intel 8008 support page] unofficial
• {{cite book |url=http://donbot.com/MicrocomputerDesign/First_Edition/F001.html |author-first=Donald P. |author-last=Martin |title=Microcomputer Design |publisher=Martin Research |date=1974}}
• {{cite book |url=http://donbot.com/MicrocomputerDesign/SE/M001.html |author-mask=1 |author-first1=Donald P. |author-last1=Martin |title=Microcomputer Design |edition=2 |date=1976 |publisher=Martin Research |oclc=911808003}}
• {{cite journal |url=https://archive.org/details/kilobaudmagazine-1977-04 |author-first=Grant |author-last=Runyan |title=Now — BASIC for the 8008 — Even! |journal=Kilobaud Magazine |date=April 1977 |pages=116–118}}
• {{cite web |url=https://archive.org/details/basiclanguageint658weav |title=A BASIC language interpreter for the Intel 8008 microprocessor |publisher=University of Illinois |date=1974}}
• [http://bitsofthegoldenage.org/download/intel-8008-reference-card/ 8008 Assembly Language Reference Card]
• {{cite web |author-first=Ken |author-last=Shirriff |title=Die photos and analysis of the revolutionary 8008 microprocessor, 45 years old |date=December 2016 |url=http://www.righto.com/2016/12/die-photos-and-analysis-of_24.html}}
• {{cite web |author-mask=1 |author-first1=Ken |author-last1=Shirriff |title=Reverse-engineering the surprisingly advanced ALU of the 8008 microprocessor |date=February 2017 |url=http://www.righto.com/2017/02/reverse-engineering-surprisingly.html}}
• {{cite web |author-mask=1 |author-first1=Ken |author-last1=Shirriff |title=How the bootstrap load made the historic Intel 8008 processor possible |date=October 2020 |url=http://www.righto.com/2020/10/how-bootstrap-load-made-historic-intel.html}}
• {{cite web |author-mask=1 |author-first1=Ken |author-last1=Shirriff |title=Reverse-engineering the carry-lookahead circuit in the Intel 8008 processor |date=November 2020 |url=http://www.righto.com/2020/11/reverse-engineering-carry-lookahead.html}}

{{Intel processors|discontinued}}

8008

Category:8-bit microprocessors

Category:Computer-related introductions in 1972