Load–store architecture

{{Short description|Type of instruction set architecture}}

In computer engineering, a load–store architecture (or a register–register architecture) is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers).

{{cite book

| title=Computer architecture: pipelined and parallel processor design

| author=Michael J. Flynn

| author-link=Michael J. Flynn

| year=1995

| publisher=Jones & Bartlett Learning

| isbn=0867202041

}}{{rp|9-12}}

Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures.{{rp|9–12}}

For instance, in a load–store approach both operands and destination for an ADD operation must be in registers. This differs from a register–memory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register.{{rp|9–12}}

The earliest example of a load–store architecture was the CDC 6600.{{rp|54–56}} Almost all vector processors (including many GPUs

{{cite web

| title=AMD GCN reference

| url=http://developer.amd.com/wordpress/media/2012/12/AMD_Southern_Islands_Instruction_Set_Architecture.pdf

}}{{Better source|reason=In need of a better source to explain how 'many' GPUs use load–store than a datasheet on a particular architecture.|date=June 2020}}) use the load–store approach.

{{cite book

| title=Memory systems and pipelined processors

| author=Harvey G. Cragon

| author-link=Harvey Cragon

| year=1996

| isbn=0867204745

| pages=512–513

| publisher=Jones & Bartlett Learning

}}