Logarithmic resistor ladder

A logarithmic resistor ladder is an electronic circuit, composed of a series of resistors and switches, designed to create an attenuation from an input to an output signal, where the logarithm of the attenuation ratio is proportional to a binary number that represents the state of the switches.

The logarithmic behavior of the circuit is its main differentiator in comparison with digital-to-analog converters (DACs) in general, and traditional R-2R Ladder networks specifically. Logarithmic attenuation is desired in situations where a large dynamic range needs to be handled. The circuit described in this article is applied in audio devices, since human perception of sound level is properly expressed on a logarithmic scale.

Logarithmic input/output behavior

As in digital-to-analog converters, a binary number is applied to the ladder network, whose N bits are treated as representing an integer value:

: $\mathrm{CodeValue} = \sum_{i=1}^N s_i \cdot 2^{i-1}$

where $s_i$ is 0 or 1 depending on the state of the i^th switch.

For comparison, recall a conventional linear DAC or R-2R network produces an output voltage signal of:

: $V_{out} = V_{in} \cdot c \cdot (\mathrm{CodeValue} + d )$

where $c$ and $d$ are design constants and where $V_{in}$ typically is a constant reference voltage (or is a variable input voltage for a multiplying DAC.{{cite web |url=http://www.analog.com/static/imported-files/overviews/AnalogMultiplyingDACs.pdf |title=Multiplying DACs, flexible building blocks |year=2010 |publisher=Analog Devices inc. |accessdate=29 March 2012}})

In contrast, the logarithmic ladder network discussed in this article creates a behavior as:

: $\log (V_{out} / V_{in}) = c \cdot \mathrm{CodeValue}$

which can also be expressed as $V_{in}$ multiplied by some base $\alpha$ raised to the power of the code value:

: $V_{out} = V_{in} \cdot \alpha ^ \mathrm{CodeValue}$

where $c = \log(\alpha) \, .$

Circuit implementation

File:Circuit_diagram_of_logarithmic_ladder_DA_converter,_Mar_2012.png

This example circuit is composed of 4 stages, numbered 1 to 4, and includes a source resistance R_source and load resistance R_load.

Each stage i has a designed input-to-output voltage attenuation Ratio_i as:

: $Ratio_i = \text{if}\; sw_i \;\text{then}\; \alpha^{2^{i-1}} \;\text{else}\; 1$

For logarithmic scaled attenuators, it is common practice to equivalently express their attenuation in decibels:

: $dB(Ratio_i) = 20 \log_{10} \alpha^{2^{i-1}} = 2^{i-1} \cdot 20 \cdot \log_{10} \alpha$ for $i = 1 .. N$ and $sw_i = 1$

This reveals a basic property: $dB(Ratio_{i+1}) = 2 \cdot dB(Ratio_i)$

To show that this $Ratio_i$ satisfies the overall intention:

: $\log (V_{out}/V_{in}) = \log (\prod_{i=1}^N Ratio_i) = \sum_{i=1}^N \log (Ratio_i) = \log (\alpha) \cdot CodeValue = c \cdot CodeValue$

The different stages 1 .. N should function independently of each other, as to obtain 2^N different states with a composable behavior. To achieve an attenuation of each stage that is independent of its surrounding stages, either one of two design choices is to be implemented: constant input resistance or constant output resistance. Because the stages operate independently, they can be inserted in the chain in any order.

= Constant input resistance =

The input resistance of any stage shall be independent of its on/off switch position, and must be equal to R_load.

This leads to:

: $\begin{cases}
R_{i,parr} = (R_{i,b} \cdot R_{load}) / (R_{i,b} + R_{load}) \\
R_{i,a} + R_{i,parr} = R_{load} \\
R_{i,parr} / (R_{i,a} + R_{i,parr}) = Ratio_i
\end{cases}$

With these equations, all resistor values of the circuit diagram follow easily after choosing values for N, $\alpha$ and R_load. (The value of R_source does not influence the logarithmic behavior)

= Constant output resistance =

The output resistance of any stage shall be independent of its on/off switch position, and must be equal to R_source.

This leads to:

: $\begin{cases}
R_{i,ser} = R_{i,a} + R_{source} \\
R_{i,ser} \cdot R_{i,b} / (R_{i,ser} + R_{i,b}) = R_{source} \\
R_{i,b} / (R_{i,ser} + R_{i,b}) = Ratio_i
\end{cases}$

Again, all resistor values of the circuit diagram follow easily after choosing values for N, $\alpha$ and R_source. (The value of R_load does not influence the logarithmic behavior).

For example, with a R_load of 1 kΩ, and 1 dB attenuation, the resistor values would be:

R_a = 108.7 Ω,

R_b = 8195.5 Ω.

The next step (2 dB) would use: R_a = 369.0 Ω,

R_b = 1709.7 Ω.

Circuit variations

The circuit as depicted above, can also be applied in reverse direction. That correspondingly reverses the role of constant-input and constant-output resistance equations.
Since the stages do not significantly influence each other's attenuation, the stage order can be chosen arbitrarily. Such reordering can have a significant effect on the input resistance of the constant output resistance attenuator and vice versa.

Background

R-2R ladder networks used for linear digital-to-analog conversion are old ({{Slink|Resistor ladder|History}} mentions a 1953 article and a 1955 patent).

Multiplying DACs with logarithmic behavior were not known for a long time after that. An initial approach was to map the logarithmic code to a much longer code word, which could be applied to the classical (linear) R-2R based DAC. Lengthening the codeword is needed in that approach to achieve sufficient dynamic range. This approach was implemented in a device from Analog Devices Inc.,{{cite web

| url = http://www.analog.com/media/en/technical-documentation/obsolete-data-sheets/1257410AD7118.pdf

| title = LOGDAC CMOS Logarithmic D/A Converter AD7118

| publisher = Analog Devices Inc.

| archive-url = https://web.archive.org/web/20150825062826/http://www.analog.com/media/en/technical-documentation/obsolete-data-sheets/1257410AD7118.pdf

| archive-date = 25 August 2015

| access-date = 25 August 2015

}} protected through a 1981 patent filing.{{cite patent |country=US |number=4521764 |status=patent |title=Signal-controllable attenuator employing a digital-to-analog converter |gdate=4 June 1985 |fdate=31 December 1981 |inventor=Burton, David P.}}

References

External links

[http://www.vaneijndhoven.net/jos/attenuator-calculator/index.html Online calculator] to configure logarithmic ladder networks

Category:Analog circuits