LowRISC
{{Short description|Not-for-profit company headquartered in Cambridge, UK}}
{{lowercase title}}
{{Infobox company
| logo = LowRISC logo.svg
| logo_caption =
| logo_alt = Red icon of circuit board traces next to the text lowRISC
| name = lowRISC C.I.C.
| type = Community Interest Company
| founded = {{Start date and age|2014|10|20}} in Cambridge, UK
| founders = Gavin Ferris, Alex Bradbury, Robert Mullins
| hq_location_city = Cambridge
| hq_location_country = United Kingdom
| products = Ibex, OpenTitan
| website = {{URL|lowrisc.org}}
}}
lowRISC C.I.C. is a not-for-profit company headquartered in Cambridge, UK. It uses collaborative engineering to develop and maintain open source silicon designs and tools.{{cite web |title=About lowRISC |url=https://www.lowrisc.org/about/ |website=lowrisc.org |access-date=24 March 2021}} lowRISC is active in RISC-V-related open source hardware and software development and stewards the OpenTitan project.
Projects
= OpenTitan =
OpenTitan is the first open source silicon Root of Trust (RoT) project.{{cite news |last1=Anderson |first1=Tim |title=Cambridge boffins and Google unveil open-source OpenTitan chip – because you never know who you can trust |url=https://www.theregister.com/2019/11/05/google_opentitan_soc_riscv/ |access-date=24 March 2021 |work=The Register |date=5 Nov 2019}} It is designed to be integrated into data center servers, storage devices, peripherals and other hardware.{{cite web |title=Open source silicon Root of Trust |url=https://opentitan.org |website=opentitan.org}} OpenTitan is under the stewardship of lowRISC and collaboratively developed by Google, ETH Zurich, Nuvoton, G+D Mobile Security, Seagate, and Western Digital.{{cite web |url=https://opentitan.org/#partners |title=OpenTitan partners | website=opentitan.org |access-date=24 March 2021}} The OpenTitan source code is available on GitHub, released under the permissive Apache 2 license.
= Ibex CPU core =
Ibex is an embedded open source 32-bit in-order RISC-V CPU core, which has been taped out multiple times.{{cite web |title=Ibex: An embedded 32 bit RISC-V CPU core |url=https://ibex-core.readthedocs.io/en/latest/index.html |access-date=24 March 2021}} Ibex is used in the OpenTitan chip.
Development on Ibex started in 2015 under the name "Zero-riscy" and "Micro-riscy" at the ETH Zurich and University of Bologna, where it was part of the PULP platform. In December 2018 lowRISC took over the development.{{cite web |title=Ibex Reference Guide: History |url=https://ibex-core.readthedocs.io/en/latest/03_reference/history.html |access-date=24 March 2021}} Luca Benini of the ETH Zurich sits on lowRISC' board.
= Prototype 64-bit SoC design =
The lowRISC prototype 64-bit SoC design is an open source Linux-capable 64-bit RISC-V SoC design. A first version preview release of the source code was made available in April 2015.{{cite web |title=lowRISC tagged memory preview release |url=https://www.lowrisc.org/blog/2015/04/lowrisc-tagged-memory-preview-release/ |website=lowrisc.org |access-date=24 March 2021 |date=April 13, 2015}} Since then features were added, such as support for tagged memory and "minion cores", small CPU cores which are dedicated to I/O tasks.{{cite web |title=Overview of the minion infrastructure |url=https://www.lowrisc.org/docs/minion-v0.4/overview/ |website=lowrisc.org |access-date=24 March 2021}} The latest version 0.6 was released in November 2018,{{cite web |title=lowRISC 0-6 milestone release |url=https://www.lowrisc.org/blog/2018/11/lowrisc-0-6-milestone-release |website=lowrisc.org |access-date=24 March 2021 |date=2018-11-12}} and is available to download and try out on an FPGA.
= Other projects =
lowRISC initiated and led the upstreaming of the RISC-V LLVM backend, where Alex Bradbury is code owner.{{cite web |last1=Bradbury |first1=Alex |title=The RISC-V LLVM backend in Clang/LLVM 9.0 |url=https://www.lowrisc.org/blog/2019/07/risc-v-llvm-backend-in-clang-llvm-9.0/ |website=lowrisc.org |access-date=24 March 2021}}
Governance
lowRISC's governance and current appointed directors are set out in its entry at the UK Companies House.
[https://find-and-update.company-information.service.gov.uk/company/09272283 lowRISC entry] on the Companies House website
History
lowRISC was spun out of the University of Cambridge Computer Lab in 2014 by Alex Bradbury, Robert Mullins, and Gavin Ferris with the goal of creating a fully open source SoC and low-cost development board.{{cite news |title=Free Core, Some Assembly Required |url=https://www.eetimes.com/free-core-some-assembly-required/ |access-date=24 March 2021 |work=EETimes |date=2016-01-07}}{{cite web |title=LowRISC SoC - 1st RISC-V Workshop |url=https://www.youtube.com/watch?v=r1i9SAOdyS4 |website=YouTube}}
In 2015 lowRISC became one of the founding members of the RISC-V Foundation (today: RISC-V International).{{cite web |title=Founding Members |url=https://riscv.org/membership/founding-members/ |website=riscv.org |access-date=24 March 2021}}
Since 2018 lowRISC has been focusing on collaborative engineering with partner organizations.
In 2019 the OpenTitan project, stewarded by lowRISC, was announced.{{cite web |last1=Bradbury |first1=Alex |title=Announcing OpenTitan, the First Transparent Silicon Root of Trust |url=https://www.lowrisc.org/blog/2019/11/announcing-opentitan-the-first-transparent-silicon-root-of-trust/ |date=2019-11-05}}