M·CORE

M·CORE is a low-power, RISC-based microcontroller architecture developed by Motorola (subsequently Freescale, now part of NXP), intended for use in embedded systems. Introduced in late 1997, the architecture combines a 32-bit internal data path with 16-bit instructions,{{Citation |url=http://www.saladeteletipos.com/pub/SistemasEmbebidos2006/PlacaMotorola/mcore_rm_1.pdf |title=M-CORE, microRISC Engine, Programmers Reference Manual |edition=Revision 1.0 |publisher=Motorola, Inc. |year=1997 |archive-url=https://web.archive.org/web/20160304090032/http://www.saladeteletipos.com/pub/SistemasEmbebidos2006/PlacaMotorola/mcore_rm_1.pdf |archive-date=2016-03-04 |url-status=dead}} and includes a four-stage instruction pipeline. Initial implementations used a 360nm process and ran at 50 MHz.

M·CORE processors[http://cache.freescale.com/files/32bit/doc/ref_manual/MMC2114.pdf MCore2114, 2113, 2112, Advanced Information] employ a von Neumann architecture with shared program and data bus—executing instructions from within data memory is possible. Motorola engineers designed M·CORE to have low power consumption and high code density.

[https://www.nxp.com/docs/en/fact-sheet/MCOREARCHBRF.pdf M•CORE Architectural Brief].

1997.