MERSI protocol
The MERSI protocol is a cache coherency and memory coherence protocol used by the PowerPC G4.{{Cite journal| last1 = Nicoletta | first1 = C.| last2 = Alvarez | first2 = J.| last3 = Barkin | first3 = E.| last4 = Chai-Chin Chao| last5 = Johnson | first5 = B. R.| last6 = Lassandro | first6 = F. M.| last7 = Patel | first7 = P.| last8 = Reid | first8 = D.| last9 = Sanchez | first9 = H.| last10 = Seigel | first10 = J.| last11 = Snyder | first11 = M.| last12 = Sullivan | first12 = S.| last13 = Taylor | first13 = S. A.| last14 = Minh Vo| title = A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect| doi = 10.1109/4.799852| journal = IEEE Journal of Solid-State Circuits| volume = 34| issue = 11| pages = 1478–1491| date=November 1999 | bibcode = 1999IJSSC..34.1478N}} The protocol consists of five states, Modified (M), Exclusive (E), Read Only or Recent (R), Shared (S) and Invalid (I). The M, E, S and I states are the same as in the MESI protocol. The R state is similar to the E state in that it is constrained to be the only clean, valid, copy of that data in the computer system. Unlike the E state, the processor is required to initially request ownership of the cache line in the R state before the processor may modify the cache line and transition to the M state. In both the MESI and MERSI protocols, the transition from the E to M is silent.US Patent 6857051, [https://patents.google.com/patent/US6857051]
For any given pair of caches, the permitted states of a given cache line are as follows:
| class=wikitable style=text-align:center
! !! M !! E !! R !! S !! I |
| M
| {{N}} || {{N}} || {{N}} || {{N}} || {{Y}} |
|---|
| E
| {{N}} || {{N}} || {{N}} || {{N}} || {{Y}} |
| R
| {{N}} || {{N}} || {{N}} || {{N}} || {{Y}} |
| S
| {{N}} || {{N}} || {{N}} || {{Y}} || {{Y}} |
| I
| {{Y}} || {{Y}} || {{Y}} || {{Y}} || {{Y}} |