Multi-level cell#Triple-level cell
{{short description|Memory cell capable of storing more than a single bit of information}}
File:Cell types SLC-PLC in comparison 20211102.svg
In electronics, a multi-level cell (MLC) is a memory cell capable of storing more than a single bit of information, compared to a single-level cell (SLC), which can store only one bit per memory cell. A memory cell typically consists of a single floating-gate MOSFET (metal–oxide–semiconductor field-effect transistor), thus multi-level cells reduce the number of MOSFETs required to store the same amount of data as single-level cells.
Triple-level cells (TLC) and quad-level cells (QLC) are versions of MLC memory, which can store three and four bits per cell respectively. The name "multi-level cell" is sometimes used specifically to refer to the "two-level cell". Overall, the memories are named as follows:
- Single-level cell or SLC (1 bit per cell)
- Multi-level cell or MLC (2 bits per cell), alternatively double-level cell or DLC
- Triple-level cell or TLC (3 bits per cell) or 3-Bit MLC
- Quad-level cell or QLC (4 bits per cell)
- Penta-level cell or PLC (5 bits per cell) – currently in development{{Cite web |date=2022-08-02 |title=Solidigm Demonstrates World's First Penta-Level Cell SSD at Flash Memory Summit |url=https://news.solidigm.com/en-WW/217006-solidigm-demonstrates-world-s-first-penta-level-cell-ssd-at-flash-memory-summit |access-date=2023-02-11 |website=Solidigm newsroom |language=en}}
Notice that this nomenclature can be misleading, since an "n-level cell" in fact uses 2n levels of charge to store n bits (see below).
Typically, as the "level" count increases, performance (speed and reliability) and consumer cost decrease; however, this correlation can vary between manufacturers.
Examples of MLC memories are MLC NAND flash, MLC PCM (phase-change memory), etc. For example, in SLC NAND flash technology, each cell can exist in one of the two states, storing one bit of information per cell. Most MLC NAND flash memory has four possible states per cell, so it can store two bits of information per cell. This reduces the amount of margin separating the states and results in the possibility of more errors. Multi-level cells that are designed for low error rates are sometimes called enterprise MLC (eMLC).
New technologies, such as multi-level cells and 3D Flash, and increased production volumes will continue to bring prices down.{{cite web |url=https://www.hyperstone.com/en/NAND-Flash-is-displacing-hard-disk-drives-1249,12728.html |title=NAND Flash is Displacing Hard Disk Drives |access-date=29 May 2018 }}
Single-level cell
Flash memory stores data in individual memory cells, which are made of floating-gate MOSFET transistors. Traditionally, each cell had two possible states (each with one voltage level), with each state representing either a one or a zero, so one bit of data was stored in each cell in so-called single-level cells, or SLC flash memory. SLC memory has the advantage of higher write speeds, lower power consumption and higher cell endurance. However, because SLC memory stores less data per cell than MLC memory, it costs more per megabyte of storage to manufacture. Due to higher transfer speeds and expected longer life, SLC flash technology is used in high-performance memory cards.
In February 2016, a study was published that showed little difference in practice between the reliability of SLC and MLC.{{Cite journal |title= Flash Reliability in Production: The Expected and the Unexpected |author1= Bianca Schroeder |author1-link= Bianca Schroeder|author2= Arif Merchant |publisher= Usenix |journal= Conference on File and Storage Technologies |date= February 22, 2016 |isbn= 9781931971287 |url= https://www.usenix.org/conference/fast16/technical-sessions/presentation/schroeder |access-date= November 3, 2016 }}
A single-level cell (SLC) flash memory may have a lifetime of about 50,000 to 100,000 program/erase cycles.{{Cite web |title=Hyperstone Blog {{!}} NAND Flash is displacing hard disk drives |url=https://www.hyperstone.com/en/NAND-Flash-is-displacing-hard-disk-drives-1249.html |access-date=2023-02-11 |website=Hyperstone GmbH |language=en}}
A single-level cell represents a 1 when almost empty and a 0 when almost full. There is a region of uncertainty (a read margin) between the two possible states at which the data stored in the cell cannot be precisely read.{{Cite web |last=Shimpi |first=Anand Lal |title=The Intel SSD 710 (200GB) Review |url=https://www.anandtech.com/show/4902/intel-ssd-710-200gb-review |access-date=2023-02-11 |website=www.anandtech.com}}
Multi-level cell
The primary benefit of MLC flash memory is its lower cost per unit of storage due to the higher data density, and memory-reading software can compensate for a larger bit error rate.[http://www.micron.com/products/nand/mlc-webinar.aspx Micron's MLC NAND Flash Webinar]. {{webarchive|url=https://web.archive.org/web/20070722200149/http://www.micron.com/products/nand/mlc-webinar.aspx |date=2007-07-22 }}. The higher error rate necessitates an error-correcting code (ECC) that can correct multiple bit errors; for example, the SandForce SF-2500 flash controller can correct up to 55 bits per 512-byte sector with an unrecoverable read error rate of less than one sector per 1017 bits read.{{Cite web |title=SandForce® SF2600 and SF2500 Enterprise datasheet |url=https://www.seagate.com/www-content/product-content/lsi-fam/enterprise-flash-controller/en-us/docs/enterprise-fsp-sf-2500-ds1828-1-1409us.pdf |access-date=2023-02-11 |website=Seagate}} The most commonly used algorithm is Bose–Chaudhuri–Hocquenghem (BCH code).{{Cite web |last=EETimes |date=2013-08-27 |title=A Tour of the Basics of Embedded NAND Flash Options |url=https://www.eetimes.com/a-tour-of-the-basics-of-embedded-nand-flash-options/ |access-date=2023-02-11 |website=EE Times}} Other drawbacks of MLC NAND are lower write speeds, lower number of program/erase cycles and higher power consumption compared to SLC flash memory.
Read speeds can also be lower for MLC NAND than SLC due to the need to read the same data at a second threshold voltage to help resolve errors. TLC and QLC devices may need to read the same data up to 4 and 8 times respectively to obtain values that are correctable by ECC.{{cite journal |last1=Peleato |display-authors=etal |title=Adaptive Read Thresholds for NAND Flash |journal=IEEE Transactions on Communications |date=Sep 2015 |volume=63 |issue=9 |pages=3069–3081 |doi=10.1109/TCOMM.2015.2453413 |s2cid=14159361|arxiv=2202.05661 }}
MLC flash may have a lifetime of about 1,000 to 10,000 program/erase cycles. This typically necessitates the use of a flash file system, which is designed around the limitations of flash memory, such as using wear leveling to extend the useful lifetime of the flash device.
The Intel 8087 used two-bits-per-cell technology for its microcode ROM,{{Cite web |title=Two bits per transistor: high-density ROM in Intel's 8087 floating point chip |url=http://www.righto.com/2018/09/two-bits-per-transistor-high-density.html |access-date=2022-05-18}} and in 1980 was one of the first devices on the market to use multi-level ROM cells."Four-state cell called density key" article by J. Robert Lineback. "Electronics" magazine. 1982 June 30.{{Cite book |last=P. Glenn Gulak |title=Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138) |date=2018-05-28 |chapter=A Review of Multiple-Valued Memory Technology |chapter-url=https://pdfs.semanticscholar.org/a3c1/cbc425c7987fe2307b48e0ff96f2c2c1b038.pdf |access-date=2023-02-11 |via=web.archive.org|pages=222–231 |doi=10.1109/ISMVL.1998.679447 |isbn=978-0-8186-8371-8 |s2cid=10931493 |archive-url=https://web.archive.org/web/20180528133902/https://pdfs.semanticscholar.org/a3c1/cbc425c7987fe2307b48e0ff96f2c2c1b038.pdf |archive-date=2018-05-28 }} Intel later demonstrated 2-bit multi-level cell (MLC) NOR flash in 1997.{{cite web |title=The Flash Memory Market |url=http://smithsonianchips.si.edu/ice/cd/MEMORY97/SEC05.PDF |website=Integrated Circuit Engineering Corporation |publisher=Smithsonian Institution |year=1997 |access-date=16 October 2019}} NEC demonstrated quad-level cells in 1996, with a 64{{nbsp}}Mbit flash memory chip storing 2 bits per cell. In 1997, NEC demonstrated a dynamic random-access memory (DRAM) chip with quad-level cells, holding a capacity of 4{{nbsp}}Gbit. STMicroelectronics also demonstrated quad-level cells in 2000, with a 64{{nbsp}}Mbit NOR flash memory chip.{{cite web |title=Memory |url=http://maltiel-consulting.com/Semiconductor_technology_memory.html |website=STOL (Semiconductor Technology Online) |access-date=25 June 2019 |archive-date=2 November 2023 |archive-url=https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html |url-status=dead }}
MLC is used to refer to cells that store 2 bits per cell, using 4 charge values or levels. A 2-bit MLC has a single charge level assigned to every possible combination of ones and zeros, as follows: When close to 25% full, the cell represents a binary value of 11; when close to 50%, the cell represents a 01; when close to 75%, the cell represents a 00; and when close to 100%, the cell represents a 10. Once again, there is a region of uncertainty (read margin) between values, at which the data stored in the cell cannot be precisely read.{{cite web |url=https://www.enterprisestorageforum.com/storage-hardware/slc-vs-mlc-vs-tlc-nand-flash.html |author=Pedro Hernandez |title=SLC vs MLC vs TLC NAND Flash |website=Enterprise Storage Forum |date=June 29, 2018}}
{{As of|2013|post=,}} some solid-state drives use part of an MLC NAND die as if it were single-bit SLC NAND, giving higher write speeds.{{Cite web |last=Gasior |first=Geoff |date=2013-07-25 |title=Samsung's 840 EVO solid-state drive reviewed |url=https://techreport.com/review/25122/samsungs-840-evo-solid-state-drive-reviewed/ |access-date=2023-02-11 |website=The Tech Report |language=en-US}}{{Cite web |date=2013-07-18 |title=New Samsung 840 EVO employs TLC and pseudo-SLC TurboWrite cache - PC Perspective |url=https://pcper.com/2013/07/new-samsung-840-evo-employs-tlc-and-pseudo-slc-turbowrite-cache/ |access-date=2023-02-11 |website=pcper.com |language=en-US}}Samsung. [http://www.samsung.com/global/business/semiconductor/samsungssd/downloads/Samsung_SSD_TurboWrite_Whitepaper.pdf "Samsung Solid State Drive: TurboWrite Technology White Paper"]. 2013.
{{As of|2018|post=,}} nearly all commercial MLCs are planar-based (i.e. cells are built on silicon surface) and so subject to scaling limitations. To address this potential problem, the industry is already looking at technologies that can guarantee storage density increases beyond today’s limitations. One of the most promising is 3D Flash, where cells are stacked vertically, thereby avoiding the limitations of planar scaling.{{Cite web |date=2018-04-17 |title=Hyperstone Blog {{!}} Solid State bit density and the Flash Memory Controller |url=https://www.hyperstone.com/en/Solid-State-bit-density-and-the-Flash-Memory-Controller-1235.html |access-date=2023-02-11 |website=Hyperstone GmbH |language=en}}
In the past, a few memory devices went the other direction and used two cells per bit to give even lower bit error rates.{{Cite web |last=Prophet |first=Graham |date=2008-10-02 |title=Automotive EEPROMs use two cells per bit for ruggedness, reliability |url=https://www.edn.com/automotive-eeproms-use-two-cells-per-bit-for-ruggedness-reliability/ |access-date=2023-02-11 |website=EDN |language=en-US}}
Enterprise MLC (eMLC) is a more expensive variant of MLC that is optimized for commercial use. It claims to last longer and be more reliable than normal MLCs while providing cost savings over traditional SLC drives. Although many SSD manufacturers have produced MLC drives intended for enterprise use, only Micron sells raw NAND Flash chips under this designation.{{cite web |title=Enterprise MLC: Extended MLC Cycling Capabilities |url=https://www.micron.com/products/nand-flash/mlc-nand/enterprise-mlc |website=www.micron.com |access-date=17 November 2019 |language=en}}
Triple-level cell
File:WDC WDS200T2B0A-00SM50 2000,3 GB SATA Vorderseite 20211008 SSD024corr.png
A triple-level cell (TLC) is a type of NAND flash memory that stores 3 bits of information per cell. Toshiba introduced memory with triple-level cells in 2009.{{cite news |title=Toshiba Makes Major Advances in NAND Flash Memory with 3-bit-per-cell 32nm generation and with 4-bit-per-cell 43nm technology |url=http://www.toshiba.co.jp/about/press/2009_02/pr1102.htm |access-date=21 June 2019 |work=Toshiba |date=11 February 2009}}
With current technology a maximum lifetime of up to 3,000 program/erase cycles is achievable.{{cite web |title=Difference between SLC, MLC, TLC and 3D NAND in USB flash drives, SSDs and Memory cards |url=https://www.kingston.com/en/blog/pc-performance/difference-between-slc-mlc-tlc-3d-nand |website=Kingston Technologies |access-date=8 February 2024 |date=May 2021}}
Samsung announced a type of NAND flash that stores 3 bits of information per cell, with 8 total voltage states (values or levels), coining the term "triple-level cell" ("TLC"). Samsung Electronics began mass-producing it in 2010,{{cite web |title=History |url=https://www.samsung.com/us/aboutsamsung/company/history/ |website=Samsung Electronics |publisher=Samsung |access-date=19 June 2019}} and it was first seen in Samsung's 840 Series SSDs.{{Cite web |url=http://www.samsung.com/global/business/semiconductor/minisite/SSD/uk/html/about/MlcNandFlash.html |title=Samsung SSD 840 Series – 3BIT/MLC NAND Flash |access-date=2013-04-10 |archive-url=https://web.archive.org/web/20130410070908/http://www.samsung.com/global/business/semiconductor/minisite/SSD/uk/html/about/MlcNandFlash.html |archive-date=2013-04-10 |url-status=live }} Samsung refers to this technology as 3-bit MLC. The negative aspects of MLC are amplified with TLC, but TLC benefits from still higher storage density and lower cost.{{cite web |url=http://www.anandtech.com/show/6459/samsung-ssd-840-testing-the-endurance-of-tlc-nand |title=Samsung SSD 840: Testing the Endurance of TLC NAND |publisher=AnandTech |date=2012-11-16 |access-date=2014-04-05}}
In 2013, Samsung introduced V-NAND (Vertical NAND, also known as 3D NAND) with triple-level cells, which had a memory capacity of 128{{nbsp}}Gbit.{{cite news |title=Samsung Mass Producing 128Gb 3-bit MLC NAND Flash |url=https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html |access-date=21 June 2019 |work=Tom's Hardware |date=11 April 2013 |archive-date=21 June 2019 |archive-url=https://web.archive.org/web/20190621175628/https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html |url-status=dead }} They expanded their TLC V-NAND technology to 256{{nbsp}}Gbit memory in 2015, and 512{{nbsp}}Gbit in 2017.{{cite news |last1=Shilov |first1=Anton |title=Samsung Starts Production of 512 GB UFS NAND Flash Memory: 64-Layer V-NAND, 860 MB/s Reads |url=https://www.anandtech.com/show/12120/samsung-starts-production-of-512-gb-ufs-chips |access-date=23 June 2019 |work=AnandTech |date=December 5, 2017}}
Enterprise TLC (eTLC) is a more expensive variant of TLC that is optimized for commercial use.
Quad-level cell
Memory that stores 4 bits per cell is commonly referred to as quad-level cell (QLC), following the convention set by TLC. Prior to its invention, the term "QLC" was synonymous with MLC in referring to cells that can have 4 voltage states, i.e. ones that store 2 bits per cell – what is now unambiguously referred to as DLC.{{cn|date=December 2022}}
Due to the exponentially increasing number of required voltage stages for higher level flash the lifetime of QLC is further reduced to a maximum of 1,000 program/erase cycles.
In 2009, Toshiba and SanDisk introduced NAND flash memory chips with quad-level cells, storing 4 bits per cell and holding a capacity of 64{{nbsp}}Gbit.{{cite news |title=SanDisk ships world's first memory cards with 64 gigabit X4 NAND flash |url=https://www.slashgear.com/sandisk-ships-worlds-first-memory-cards-with-64-gigabit-x4-nand-flash-1360217/ |access-date=20 June 2019 |work=SlashGear |date=13 October 2009}}
SanDisk X4 flash memory cards, introduced in 2009, was one of the first products based on NAND memory that stores 4 bits per cell, commonly referred to as quad-level-cell (QLC), using 16 discrete charge levels (states) in each individual transistor. The QLC chips used in these memory cards were manufactured by Toshiba, SanDisk and SK Hynix.{{Cite web |last=McGlaun |first=Shane |date=2009-10-13 |title=SanDisk Ships World's First Memory Cards With 64 Gigabit X4 NAND Flash |url=https://www.slashgear.com/sandisk-ships-worlds-first-memory-cards-with-64-gigabit-x4-nand-flash-1360217/ |access-date=2023-02-11 |website=SlashGear |language=en-US}}{{Cite web |last=Choi |first=Young |date=2009-05-05 |title=NAND Flash - The New Era of 4 bit per cell and Beyond |url=https://www.eetimes.com/nand-flash-45-the-new-era-of-4-bit-per-cell-and-beyond/ |access-date=2023-02-11 |website=EE Times}}
In 2017, Toshiba introduced V-NAND memory chips with quad-level cells, which have a storage capacity of up to 768{{nbsp}}Gbit.{{cite news |title=Toshiba Develops World's First 4-bit Per Cell QLC NAND Flash Memory |url=https://www.techpowerup.com/234729/toshiba-develops-worlds-first-4-bit-per-cell-qlc-nand-flash-memory |access-date=20 June 2019 |work=TechPowerUp |date=June 28, 2017}} In 2018, ADATA, Intel, Micron and Samsung have launched some SSD products using QLC NAND memory.{{Cite web|url=https://www.anandtech.com/show/13606/adata-ultimate-su630-ssd-3d-qlc-for-sata|title=ADATA Reveals Ultimate SU630 SSD: 3D QLC for SATA|last=Shilov|first=Anton|website=AnandTech.com|access-date=2019-05-13}}{{Cite web|url=https://www.anandtech.com/show/13078/the-intel-ssd-660p-ssd-review-qlc-nand-arrives|title=The Intel SSD 660p SSD Review: QLC NAND Arrives For Consumer SSDs|last=Tallis|first=Billy|website=www.anandtech.com|access-date=2019-05-13}}{{Cite web|url=https://www.anandtech.com/show/13512/the-crucial-p1-1tb-ssd-review|title=The Crucial P1 1TB SSD Review: The Other Consumer QLC SSD|last=Tallis|first=Billy|website=www.anandtech.com|access-date=2019-05-13}}{{Cite web|url=https://www.anandtech.com/show/13170/samsung-starts-mass-production-of-qlc-vnandbased-ssds|title=Samsung Starts Mass Production of QLC V-NAND-Based SSDs|last=Shilov|first=Anton|website=AnandTech.com|access-date=2019-05-13}}
In 2020, Samsung released a QLC SSD with storage space up to 8 TB for customers. It is the SATA SSD with the largest storage capacity for consumers as of 2020.{{Cite web |title=Samsung 870 QVO SATA 2.5" SSD |url=https://semiconductor.samsung.com/consumer-storage/internal-ssd/870qvo |access-date=2023-02-11 |website=Samsung Semiconductor Global |language=en}}{{cite web |url=https://news.samsung.com/global/samsung-electronics-debuts-industry-leading-8tb-consumer-ssd-the-870-qvo |title=Samsung Electronics Debuts Industry-Leading 8TB Consumer SSD, the 870 QVO |website=Samsung Newsroom}}
Enterprise QLC (eQLC) is a more expensive variant of QLC that is optimized for commercial use.
See also
References
{{Reflist}}
External links
- [http://www.linux-mtd.infradead.org/doc/nand.html Linux Memory Technology Devices - NAND]
- [http://www.onfi.org Open NAND Flash Interface]