NAND logic

{{main|NAND gate}}

A NAND gate is an inverted AND gate. It has the following truth table:

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File:CMOS_NAND.svg transistor NAND element. V_dd denotes positive voltage.]]

In CMOS logic, if both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and Vdd (voltage source), bringing the output high. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high. As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a NAND (NOT AND) logic gate.

A NAND gate is a universal gate, meaning that any other gate can be represented as a combination of NAND gates.

{{see also|NOT gate}}

A NOT gate is made by joining the inputs of a NAND gate together. Since a NAND gate is equivalent to an AND gate followed by a NOT gate, joining the inputs of a NAND gate leaves only the NOT gate.

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{{see also|AND gate}}

An AND gate is made by inverting the output of a NAND gate as shown below.

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{{see also|OR gate}}

If the truth table for a NAND gate is examined or by applying De Morgan's laws, it can be seen that if any of the inputs are 0, then the output will be 1. To be an OR gate, however, the output must be 1 if any input is 1. Therefore, if the inputs are inverted, any high input will trigger a high output.

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{{see also|NOR gate}}

A NOR gate is an OR gate with an inverted output. Output is high when neither input A nor input B is high.

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{{see also|XOR gate}}

An XOR gate is made by connecting four NAND gates as shown below. This construction entails a propagation delay three times that of a single NAND gate.

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Alternatively, an XOR gate is made by considering the disjunctive normal form $A\; \backslash cdot\; \backslash overline\{B\}\; +\; \backslash overline\{A\}\; \backslash cdot\; B$, noting from de Morgan's law that a NAND gate is an inverted-input OR gate. This construction uses five gates instead of four.

{{see also|XNOR gate}}

An XNOR gate is made by considering the disjunctive normal form $A\; \backslash cdot\; B\; +\; \backslash overline\{A\}\; \backslash cdot\; \backslash overline\{B\}$, noting from de Morgan's law that a NAND gate is an inverted-input OR gate. This construction entails a propagation delay three times that of a single NAND gate and uses five gates.

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Alternatively, the 4-gate version of the XOR gate can be used with an inverter. This construction has a propagation delay four times (instead of three times) that of a single NAND gate.

A multiplexer or a MUX gate is a three-input gate that uses one of the inputs, called the selector bit, to select one of the other two inputs, called data bits, and outputs only the selected data bit.{{cite book |last1=Nisan |first1=Noam |author-link1=Noam Nisan |last2=Schocken |first2=Shimon |date=2005 |title=From NAND to Tetris: Building a Modern Computer from First Principles |publisher=The MIT Press |chapter=1. Boolean Logic |url=http://www.nand2tetris.org/chapters/chapter%2001.pdf |archive-url=https://web.archive.org/web/20170110185621/http://www.nand2tetris.org/chapters/chapter%2001.pdf |archive-date=2017-01-10}}

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A demultiplexer performs the opposite function of a multiplexer: It takes a single input and channels it to one of two possible outputs according to a selector bit that specifies which output to choose.{{Copyright violation|date=April 2024}}

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• CMOS transistor structures and chip deposition geometries that produce NAND logic elements
• Sheffer stroke – other name
• NOR logic – like NAND gates, NOR gates are also universal gates
• Functional completeness

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• {{cite book | last = Lancaster | first = Don | authorlink = Don Lancaster | title = TTL Cookbook | publisher = Howard W Sams | edition = 1st | year = 1974 | location = Indianapolis, IN | pages = [https://archive.org/details/ttlcookbook00lanc/page/126 126–135] | isbn = 0-672-21035-5 | url-access = registration | url = https://archive.org/details/ttlcookbook00lanc/page/126 }}
• {{citation|first=H. M.|last= Sheffer|year= 1913|title=A set of five independent postulates for Boolean algebras, with application to logical constants|journal=Transactions of the American Mathematical Society |volume=14|issue= 4|pages=481–488|jstor=1988701|doi=10.2307/1988701|doi-access=free}}

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• [http://www.allaboutcircuits.com/vol_4/chpt_3/5.html TTL NAND and AND gates] – All About Circuits
• {{webarchive |url=https://web.archive.org/web/20240611122229/https://www.fullchipdesign.com/drive_xor_nand_interview.htm |date=June 11, 2024 |title=Drive XOR using either NAND gates or NOR gates.}}
• [https://nandgame.com/ NandGame] – a game about building a computer using only NAND gates

Category:Logic gates