NAND logic

{{Short description|Logic constructed only from NAND gates}}

{{about|NAND logic in the sense of building other logic gates using just NAND gates|NAND gates|NAND gate|NAND in the purely logical sense|Logical NAND|logic gates generally|Logic gate}}The NAND Boolean function has the property of functional completeness. This means that any Boolean expression can be re-expressed by an equivalent expression utilizing only NAND operations. For example, the function NOT(x) may be equivalently expressed as NAND(x,x). In the field of digital electronic circuits, this implies that it is possible to implement any Boolean function using just NAND gates.

The mathematical proof for this was published by Henry M. Sheffer in 1913 in the Transactions of the American Mathematical Society (Sheffer 1913). A similar case applies to the NOR function, and this is referred to as NOR logic.

NAND

{{main|NAND gate}}

A NAND gate is an inverted AND gate. It has the following truth table:

style="margin:auto; text-align:center;"
Image:NAND ANSI Labelled.svg
colspan="2" style="text-align:center;"|

Q = A NAND B

{| class="wikitable" style="text-align:center; margin:auto;"

|+Truth Table

! Input A !! Input B !! Output Q

001
011
101
110

|}

File:CMOS_NAND.svg transistor NAND element. Vdd denotes positive voltage.]]

In CMOS logic, if both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and Vdd (voltage source), bringing the output high. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high. As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a NAND (NOT AND) logic gate.

Making other gates by using NAND gates

A NAND gate is a universal gate, meaning that any other gate can be represented as a combination of NAND gates.

=NOT=

{{see also|NOT gate}}

A NOT gate is made by joining the inputs of a NAND gate together. Since a NAND gate is equivalent to an AND gate followed by a NOT gate, joining the inputs of a NAND gate leaves only the NOT gate.

style="margin:auto; text-align:center;"
width=150|Desired NOT Gatewidth=150|NAND Construction
Image:NOT ANSI Labelled.svgImage:NOT from NAND.svg
Q = NOT( A )= A NAND A
colspan="2" style="text-align:center;"|

{| class="wikitable" style="text-align:center; margin:auto;"

|+Truth Table

! Input A !! Output Q

01
10

|}

=AND=

{{see also|AND gate}}

An AND gate is made by inverting the output of a NAND gate as shown below.

style="margin:auto; text-align:center;"
width=150|Desired AND Gatewidth=150|NAND Construction
Image:AND ANSI Labelled.svgImage:AND from NAND.svg
class="nowrap"

|Q = A AND B

= ( A NAND B ) NAND ( A NAND B )
colspan="2" style="text-align:center;"|

{| class="wikitable" style="text-align:center; margin:auto;"

|+Truth Table

! Input A !! Input B !! Output Q

000
010
100
111

|}

=OR=

{{see also|OR gate}}

If the truth table for a NAND gate is examined or by applying De Morgan's laws, it can be seen that if any of the inputs are 0, then the output will be 1. To be an OR gate, however, the output must be 1 if any input is 1. Therefore, if the inputs are inverted, any high input will trigger a high output.

style="margin:auto; text-align:center;"
width=150|Desired OR Gatewidth=150|NAND Construction
Image:OR ANSI Labelled.svgImage:OR from NAND.svg
class="nowrap"

|Q = A OR B

= ( A NAND A ) NAND ( B NAND B )
colspan="2" style="text-align:center;"|

{| class="wikitable" style="text-align:center; margin:auto;"

|+Truth Table

! Input A !! Input B !! Output Q

000
011
101
111

|}

=NOR=

{{see also|NOR gate}}

A NOR gate is an OR gate with an inverted output. Output is high when neither input A nor input B is high.

style="margin:auto; text-align:center;"
width=150|Desired NOR Gatewidth=150|NAND Construction
Image:NOR ANSI Labelled.svgImage:NOR from NAND.svg
class="nowrap"

|Q = A NOR B

= [ ( A NAND A ) NAND ( B NAND B ) ] NAND
[ ( A NAND A ) NAND ( B NAND B ) ]
colspan="2" style="text-align:center;"|

{| class="wikitable" style="text-align:center; margin:auto;"

|+Truth Table

! Input A !! Input B !! Output Q

001
010
100
110

|}

=XOR=

{{see also|XOR gate}}

An XOR gate is made by connecting four NAND gates as shown below. This construction entails a propagation delay three times that of a single NAND gate.

style="margin:auto; text-align:center;"
width=150|Desired XOR Gatewidth=150|NAND Construction
Image:XOR ANSI Labelled.svgImage:XOR from NAND.svg
class="nowrap"

|Q = A XOR B

= [ A NAND ( A NAND B ) ] NAND
[ B NAND ( A NAND B ) ]
colspan="2" style="text-align:center;"|

{| class="wikitable" style="text-align:center; margin:auto;"

|+Truth Table

! Input A !! Input B !! Output Q

000
011
101
110

|}

Alternatively, an XOR gate is made by considering the disjunctive normal form A \cdot \overline{B} + \overline{A} \cdot B, noting from de Morgan's law that a NAND gate is an inverted-input OR gate. This construction uses five gates instead of four.

align=center style="text-align:center"

!width=150|Desired Gate!!width=150|NAND Construction

Image:XOR ANSI Labelled.svgImage:XOR from NAND 2.svg
class="nowrap"

|Q = A XOR B

= [ B NAND ( A NAND A ) ] NAND
[ A NAND ( B NAND B ) ]

=XNOR=

{{see also|XNOR gate}}

An XNOR gate is made by considering the disjunctive normal form A \cdot B + \overline{A} \cdot \overline{B}, noting from de Morgan's law that a NAND gate is an inverted-input OR gate. This construction entails a propagation delay three times that of a single NAND gate and uses five gates.

style="margin:auto; text-align:center;"
width=150|Desired XNOR Gatewidth=150|NAND Construction
Image:XNOR ANSI Labelled.svgImage:XNOR from NAND 2.svg
class="nowrap"

|Q = A XNOR B

= [ ( A NAND A ) NAND ( B NAND B ) ] NAND
( A NAND B )
colspan="2" |

{| class="wikitable" style="text-align:center; margin:auto;"

! Input A !! Input B !! Output Q

001
010
100
111

|}

Alternatively, the 4-gate version of the XOR gate can be used with an inverter. This construction has a propagation delay four times (instead of three times) that of a single NAND gate.

align=center style="text-align:center"

!width=150|Desired Gate!!width=150|NAND Construction

Image:XNOR ANSI Labelled.svgImage:XNOR from NAND.svg
class="nowrap"

|Q = A XNOR B

= { [ A NAND ( A NAND B ) ] NAND
[ B NAND ( A NAND B ) ] } NAND
{ [ A NAND ( A NAND B ) ]
NAND [ B NAND ( A NAND B ) ] }

MUX

A multiplexer or a MUX gate is a three-input gate that uses one of the inputs, called the selector bit, to select one of the other two inputs, called data bits, and outputs only the selected data bit.{{cite book |last1=Nisan |first1=Noam |author-link1=Noam Nisan |last2=Schocken |first2=Shimon |date=2005 |title=From NAND to Tetris: Building a Modern Computer from First Principles |publisher=The MIT Press |chapter=1. Boolean Logic |url=http://www.nand2tetris.org/chapters/chapter%2001.pdf |archive-url=https://web.archive.org/web/20170110185621/http://www.nand2tetris.org/chapters/chapter%2001.pdf |archive-date=2017-01-10}}

style="margin:auto; text-align:center;"
width="200"|Desired MUX Gatewidth="200"|NAND Construction
Q = [ A AND NOT( S ) ]
OR ( B AND S )
= [ A NAND ( S NAND S ) ]
NAND ( B NAND S )
File:MUX_Diagram_using_NAND_Gates.png
colspan="2" |

{| class="wikitable" style="text-align:center; margin:auto;"

|+Truth Table

! Input A !! Input B !!Select

!Output Q

000

|0

010

|0

100

|1

110

|1

0

|0

|1

|0

0

|1

|1

|1

1

|0

|1

|0

1

|1

|1

|1

|}

DEMUX

A demultiplexer performs the opposite function of a multiplexer: It takes a single input and channels it to one of two possible outputs according to a selector bit that specifies which output to choose.{{Copyright violation|date=April 2024}}

style="margin:auto; text-align:center;"
width="150" |Desired DEMUX Gatewidth="150" |NAND Construction
DEMUX Gate
colspan="2" |

{| class="wikitable" style="text-align:center; margin:auto;"

|+Truth Table

! Input !! Select

! Output A !! Output B

0

|0

|0

|0

1

|0

|1

|0

0

|1

|0

|0

1

|1

|0

|1

|}

See also

References

{{reflist}}

{{refbegin}}

  • {{cite book | last = Lancaster | first = Don | authorlink = Don Lancaster | title = TTL Cookbook | publisher = Howard W Sams | edition = 1st | year = 1974 | location = Indianapolis, IN | pages = [https://archive.org/details/ttlcookbook00lanc/page/126 126–135] | isbn = 0-672-21035-5 | url-access = registration | url = https://archive.org/details/ttlcookbook00lanc/page/126 }}
  • {{citation|first=H. M.|last= Sheffer|year= 1913|title=A set of five independent postulates for Boolean algebras, with application to logical constants|journal=Transactions of the American Mathematical Society |volume=14|issue= 4|pages=481–488|jstor=1988701|doi=10.2307/1988701|doi-access=free}}

{{refend}}