Network interface controller

The network controller implements the electronic circuitry required to communicate using a specific physical layer and data link layer standard such as Ethernet or Wi-Fi.{{efn|Although other network technologies exist, Ethernet (IEEE 802.3) and Wi-Fi (IEEE 802.11) have achieved near-ubiquity as LAN technologies since the mid-1990s.}} This provides a base for a full network protocol stack, allowing communication among computers on the same local area network (LAN) and large-scale network communications through routable protocols, such as Internet Protocol (IP).

The NIC allows computers to communicate over a computer network, either by using cables or wirelessly. The NIC is both a physical layer and data link layer device, as it provides physical access to a networking medium and, for IEEE 802 and similar networks, provides a low-level addressing system through the use of MAC addresses that are uniquely assigned to network interfaces.

File:12 early PC network cards.jpg.]]

File:Intel Ophir 82571 Dual Port Gigabit Ethernet Controller Die Shot.png]]

Network controllers were originally implemented as expansion cards that plugged into a computer bus. The low cost and ubiquity of the Ethernet standard means that most new computers have a network interface controller built into the motherboard. Newer server motherboards may have multiple network interfaces built-in. The Ethernet capabilities are either integrated into the motherboard chipset or implemented via a low-cost dedicated Ethernet chip. A separate network card is typically no longer required unless additional independent network connections are needed or some non-Ethernet type of network is used. A general trend in computer hardware is towards integrating the various components of systems on a chip, and this is also applied to network interface cards.

An Ethernet network controller typically has an 8P8C socket where the network cable is connected. Older NICs also supplied BNC, or AUI connections. Ethernet network controllers typically support 10 Mbit/s Ethernet, 100 Mbit/s Ethernet, and Gigabit Ethernet varieties. Such controllers are designated as 10/100/1000, meaning that they can support data rates of 10, 100 or {{nowrap|1000 Mbit/s}}. 10 Gigabit Ethernet NICs are also available, and, {{As of|2014|11|lc=yes}}, are beginning to be available on computer motherboards.{{cite web |url=http://www.networkcomputing.com/networking/will-2014-be-the--year-of-10-gigabit-ethernet/a/d-id/1234640? |title=Will 2014 Be The Year Of 10 Gigabit Ethernet? |author=Jim O'Reilly |publisher=Network Computing |date=2014-01-22 |access-date=2015-04-29}}{{cite web |url=http://www.asrock.com/news/index.asp?id=2517 |title=Breaking Speed Limits with ASRock X99 WS-E/10G and Intel 10G BASE-T LANs |website=asrock.com |date=24 November 2014 |access-date=19 May 2015}}

File:Qle3442-cu 10gbe nic.jpg QLE3442-CU SFP+ dual-port NIC]]

Modular designs like SFP and SFP+ are highly popular, especially for fiber-optic communication. These define a standard receptacle for media-dependent transceivers, so users can easily adapt the network interface to their needs.

LEDs adjacent to or integrated into the network connector inform the user of whether the network is connected, and when data activity occurs.

The NIC may include ROM to store its factory-assigned MAC address.{{cite web |url=https://www.itprotoday.com/cloud-computing/how-can-i-change-network-adapter-cards-mac-address |title=How can I change a network adapter card's MAC address? |author=John Savill |date=Nov 12, 2000 |access-date=2023-11-06}}

The NIC may use one or more of the following techniques to indicate the availability of packets to transfer:

• Polling is where the CPU examines the status of the peripheral under program control.
• Interrupt-driven I/O is where the peripheral alerts the CPU that it is ready to transfer data.

NICs may use one or more of the following techniques to transfer packet data:

• Programmed input/output, where the CPU moves the data to or from the NIC to memory.
• Direct memory access (DMA), where a device other than the CPU assumes control of the system bus to move data to or from the NIC to memory. This removes load from the CPU but requires more logic on the card. In addition, a packet buffer on the NIC may not be required and latency can be reduced.

File:ForeRunnerLE 25 ATM Network Interface (1).jpg (ATM) network interface]]

File:An Intel 82574L Gigabit Ethernet NIC, PCI Express x1 card.jpg 82574L Gigabit Ethernet NIC, a PCI Express ×1 card, which provides two hardware receive queues{{cite web

| url = http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf

| title = Intel 82574 Gigabit Ethernet Controller Family Datasheet

| date = June 2014 | access-date = November 16, 2014

| publisher = Intel | page = 1

}}]]

Multiqueue NICs provide multiple transmit and receive queues, allowing packets received by the NIC to be assigned to one of its receive queues. The NIC may distribute incoming traffic between the receive queues using a hash function. Each receive queue is assigned to a separate interrupt; by routing each of those interrupts to different CPUs or CPU cores, processing of the interrupt requests triggered by the network traffic received by a single NIC can be distributed improving performance.{{cite web

| url = https://www.kernel.org/doc/Documentation/networking/scaling.txt

| title = Linux kernel documentation: Documentation/networking/scaling.txt

| date = May 9, 2014 | access-date = November 16, 2014

| author1 = Tom Herbert | author2 = Willem de Bruijn

| publisher = kernel.org

}}{{cite web

| url = http://www.mouser.com/pdfdocs/i210brief.pdf

| title = Intel Ethernet Controller i210 Family Product Brief

| year = 2012 | access-date = November 16, 2014

| publisher = Intel }}

The hardware-based distribution of the interrupts, described above, is referred to as receive-side scaling (RSS).{{cite web

| url = http://www.intel.com/content/dam/technology-provider/secure/us/en/documents/product-marketing-information/tst-grantley-launch-presentation-2014.pdf

| title = Intel Look Inside: Intel Ethernet

| work = Xeon E5 v3 (Grantley) Launch

| date = November 27, 2014 | access-date = March 26, 2015

| publisher = Intel

| archive-url = https://web.archive.org/web/20150326095816/http://www.intel.com/content/dam/technology-provider/secure/us/en/documents/product-marketing-information/tst-grantley-launch-presentation-2014.pdf

| archive-date = March 26, 2015

}}{{rp|82}} Purely software implementations also exist, such as the receive packet steering (RPS), receive flow steering (RFS), and Intel Flow Director.{{rp|98,99}}{{cite web

| url = https://www.kernel.org/doc/Documentation/networking/ixgbe.txt

| title = Linux kernel documentation: Documentation/networking/ixgbe.txt

| date = December 15, 2014 | access-date = March 26, 2015

| publisher = kernel.org

}}{{cite web

| url = http://www.intel.com/content/www/us/en/ethernet-controllers/ethernet-flow-director-video.html

| title = Intel Ethernet Flow Director

| date = February 16, 2015 | access-date = March 26, 2015

| publisher = Intel

}}{{cite web

| url = http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/intel-ethernet-flow-director.pdf

| title = Introduction to Intel Ethernet Flow Director and Memcached Performance

| date = October 14, 2014 | access-date = October 11, 2015

| publisher = Intel }} Further performance improvements can be achieved by routing the interrupt requests to the CPUs or cores executing the applications that are the ultimate destinations for network packets that generated the interrupts. This technique improves locality of reference and results in higher overall performance, reduced latency and better hardware utilization because of the higher utilization of CPU caches and fewer required context switches.

With multi-queue NICs, additional performance improvements can be achieved by distributing outgoing traffic among different transmit queues. By assigning different transmit queues to different CPUs or CPU cores, internal operating system contentions can be avoided. This approach is usually referred to as transmit packet steering (XPS).

Some products feature NIC partitioning (NPAR, also known as port partitioning) that uses SR-IOV virtualization to divide a single 10 Gigabit Ethernet NIC into multiple discrete virtual NICs with dedicated bandwidth, which are presented to the firmware and operating system as separate PCI device functions.{{cite web

| url = http://www.dell.com/downloads/global/products/pedge/en/Dell-Broadcom-NPAR-White-Paper.pdf

| title = Enhancing Scalability Through Network Interface Card Partitioning

| date = April 2011 | access-date = May 12, 2014

| publisher = Dell }}{{cite web

| url = http://www.intel.com/content/dam/www/public/us/en/documents/solution-briefs/10-gbe-ethernet-flexible-port-partitioning-brief.pdf

| title = An Introduction to Intel Flexible Port Partitioning Using SR-IOV Technology

| date = September 2011 | access-date = September 24, 2015

| author1 = Patrick Kutch | author2 = Brian Johnson | author3 = Greg Rose

| publisher = Intel }}

Some NICs provide a TCP offload engine to offload processing of the entire TCP/IP stack to the network controller. It is primarily used with high-speed network interfaces, such as Gigabit Ethernet and 10 Gigabit Ethernet, for which the processing overhead of the network stack becomes significant.{{cite web

| url = https://lwn.net/Articles/243949/

| title = Large receive offload

| date = August 1, 2007 | access-date = May 2, 2015

| author = Jonathan Corbet | publisher = LWN.net

}}

{{Anchor|SOLARFLARE|OPENONLOAD|USER-LEVEL-NETWORKING}}

Some NICs offer integrated field-programmable gate arrays (FPGAs) for user-programmable processing of network traffic before it reaches the host computer, allowing for significantly reduced latencies in time-sensitive workloads.{{cite web|title=High Performance Solutions for Cyber Security|url=http://newwavedv.com/markets/defense/cyber-security/|website=New Wave Design & Verification|publisher=New Wave DV}} Moreover, some NICs offer complete low-latency TCP/IP stacks running on integrated FPGAs in combination with userspace libraries that intercept networking operations usually performed by the operating system kernel; Solarflare's open-source OpenOnload network stack that runs on Linux is an example. This kind of functionality is usually referred to as user-level networking.{{cite web

| url = https://www.theregister.co.uk/2012/02/08/solarflare_application_onload_engine/

| title = Solarflare turns network adapters into servers: When a CPU just isn't fast enough

| date = 2012-02-08 | access-date = 2014-05-08

| author = Timothy Prickett Morgan | website = The Register

}}{{cite web

| url = http://www.openonload.org/

| title = OpenOnload

| date = 2013-12-03 | access-date = 2014-05-08

| website = openonload.org

}}{{cite web

| url = http://www.openonload.org/openonload-google-talk.pdf

| title = OpenOnload: A user-level network stack

| date = 2008-03-21 | access-date = 2014-05-08

| author1 = Steve Pope | author2 = David Riddoch

| website = openonload.org }}

• Converged network adapter (CNA)
• Host adapter
• Intel Data Direct I/O (DDIO)
• Loopback interface
• Network monitoring interface card (NMIC)
• Virtual network interface (VIF)
• Wireless network interface controller (WNIC)

{{Notelist}}

{{Reflist}}

• {{cite web |url=https://technet.microsoft.com/en-us/library/dd392944(v=ws.10).aspx |title=Physical Network Interface |publisher=Microsoft}}
• {{cite web |url=http://www.freedesktop.org/wiki/Software/systemd/PredictableNetworkInterfaceNames/ |title=Predictable Network Interface Names |website=Freedesktop.org}}
• [https://greenhost.nl/2013/04/10/multi-queue-network-interfaces-with-smp-on-linux/ Multi-queue network interfaces with SMP on Linux]

{{Basic computer components}}

Category:Ethernet

Category:Networking hardware