OpenPIC and MPIC

In order to compete with Intel's Advanced Programmable Interrupt Controller (APIC), which had enabled the first Intel 486-based multiprocessor systems, in early 1995 AMD and Cyrix proposed as somewhat similar-in-purpose OpenPIC architecture supporting up to 32 processors.{{cite web|url=https://www.pcmag.com/encyclopedia_term/0,2542,t=OpenPIC&i=48497,00.asp |title=OpenPIC Definition from PC Magazine Encyclopedia |publisher=Pcmag.com |date=1994-12-01 |accessdate=2011-11-03}}AMD and Cyrix, [https://web.archive.org/web/20180817035617/http://mess.redump.net/_media/datasheets/chrp/19725c_opic_spec_1.2_oct95.pdf The Open Programmable Interrupt Controller (PIC) Register Interface Specification Revision 1.2], October 1995. Archived from the [http://mess.redump.net/_media/datasheets/chrp/19725c_opic_spec_1.2_oct95.pdf original] on 17 Aug 2018. The OpenPIC architecture had at least declarative support from IBM and Compaq around 1995.{{cite book|title=AMD, Cyrix offer up alternative SMP spec|author=Brooke Crothers|publisher=InfoWorld|url=https://books.google.com/books?id=lToEAAAAMBAJ&pg=PA8|date=20 March 1995|page=8|issn=0199-6649}} No x86 motherboard was released with OpenPIC however.André D. Balsa, [http://linuxgazette.net/issue24/Article3e-7.html Note attached to "Linux Benchmarking: Part III -- Interpreting Benchmark Results"] appearing in Issue 24 of Linux Gazette, January 1998 After the OpenPIC's failure in the x86 market, AMD licensed the Intel APIC Architecture for its AMD Athlon and later processors.

IBM however developed their Multiprocessor Interrupt Controller (MPIC) based on the OpenPIC register specification. In the reference IBM design, the processors share the MPIC over a DCR bus, with their access to the bus controlled by a DCR Arbiter. MPIC supports up to four processors and up to 128 interrupt sources.IBM [https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/$file/mpic_db_05_16_2011.pdf Multiprocessor Interrupt Controller. Data Book] {{Webarchive|url=https://web.archive.org/web/20140223012746/https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/%24file/mpic_db_05_16_2011.pdf |date=2014-02-23 }} Through various implementations, the MPIC was included in PowerPC reference designs and some retail computers.

IBM used a MPIC based on OpenPIC 1.0 in their RS/6000 F50 and one based on OpenPIC 1.2 in their RS/6000 S70. Both of these systems also used a dual 8259 on their PCI-ISA bridges.Arca Systems TTAP Evaluation Facility, "[http://www.ashtonlabs.com/library/FERs/CSC-FER-98-004.pdf The IBM Corporation RS/6000 Distributed System Running AIX Version 4.3.1. TCSEC Evaluated C2 Security]", p. 29 An IBM MPIC was also used in the RS/6000 7046 Model B50.RS/6000 7046 Model B50 Handbook, November 1999, IBM document G24-7046-00, p. 107

The Apple Hydra Mac I/O (MIO) chip (from the 1990s classic Mac OS era) implemented a MPIC alongside a SCSI controller, ADB controller, GeoPort controller, and timers.[http://cache.freescale.com/files/archives/doc/ref_manual/YKNIFEX4HW.pdf Yellowknife Reference Platform Hardware Design Manual], p. 11 The Apple implementation of "Open PIC" (as the Apple documentation of this era spells it) in their first MIO chip for the Common Hardware Reference Platform was based on version 1.2 of the register specification and supported up to two processors and up to 20 interrupt sources.Macintosh Technology in the Common Hardware Reference Platform, section "2.4.7 Open PIC Interrupt Controller", p. 11, {{ISBN|155860393X}} A MPIC was also incorporated in the newer K2 I/O controller used in the Power Mac G5s.[http://www.informit.com/articles/article.aspx?p=606582 Take a Look Inside the G5-Based Dual-Processor Power Mac][https://web.archive.org/web/20140222145839/https://developer.apple.com/legacy/library/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/PowerMacG5.pdf Power Mac G5 Developer Note (Legacy)], p. 26

Freescale also uses a MPIC ("compatible with the Open PIC") on all its PowerQUICC and QorIQ processors.[https://www.kernel.org/doc/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt Freescale MPIC Interrupt Controller Node] The Linux Kernel-based Virtual Machine (KVM) supports a virtualized MPIC with up to 256 interrupts, based on the Freescale variants.{{cite web|url=https://github.com/torvalds/linux/blob/master/Documentation/virtual/kvm/devices/mpic.txt |title=linux/Documentation/virtual/kvm/devices/mpic.txt at master |publisher=Github.com |date=2013-04-30 |accessdate=2014-02-12}}