Open JTAG

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{{Infobox software

| name = Open JTAG

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| author = Ruben Mileca

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| repo = {{URL|https://opencores.org/websvn/listing/openjtag-project}}

| programming language = VHDL

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| license = LGPL

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| website = {{URL|www.openjtag.org}}{{Dead link|date=September 2019}}

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The Open JTAG project is an open source project released under GNU License.

It is a complete hardware and software JTAG reference design, based on a simple hardware composed by a FTDI FT245 USB front-end and an Altera EPM570 MAX II CPLD. The capabilities of this hardware configuration make the Open JTAG device able to output TCK signals at 24 MHz using macro-instructions sent from the host end.

The scope is to give the community a JTAG device not based on the PC parallel port: Open JTAG uses the USB channel to communicate with the internal CPLD, sending macro-instructions as fast as possible. The complete project (Beta version) is available at OpenCores.org[http://opencores.org/project,openjtag-project OpenCores Open JTAG project] and the Open JTAG project official site.{{Cite web |url=http://www.openjtag.org/ |title=Open JTAG official site |access-date=2010-07-26 |archive-url=https://web.archive.org/web/20100703161410/http://www.openjtag.org/ |archive-date=2010-07-03 |url-status=dead }}