PA-7100
The PA-7100 is a microprocessor developed by Hewlett-Packard (HP) that implemented the PA-RISC 1.1 instruction set architecture (ISA). It is also known as the PCX-T and by its code name Thunderbird. It was introduced in early 1992 and was the first PA-RISC microprocessor to integrate the floating-point unit (FPU) on-die. It operated at {{nowrap|33 – 100 MHz}} and competed primarily with the Digital Equipment Corporation (DEC) Alpha 21064 in the workstation and server markets. PA-7100 users were HP in its HP 9000 workstations and Stratus Computer in its Continuum fault-tolerant servers. Samsung also introduced workstations running HP-UX based on the PA-7100 and system technology licensed from HP.{{ cite news | url=https://archive.org/details/UnigramX1993417-467/page/n87/mode/1up | title=Samsung Has First HP Clone | work=Unigram/X | date=22 March 1993 | access-date=19 December 2024 | pages=2 }}
It was based on the PA-7000 (PCX-S) chip set, a previous PA-RISC implementation consisting of a microprocessor and FPU. The PA-7100 contains {{nowrap|850 000 transistors}} and measures {{nowrap|14.3 x 14.3 mm}} for an area of {{nowrap|204.49 mm².}} It was fabricated by HP in their CMOS26B process, a {{nowrap|0.8 μm}} complementary metal–oxide–semiconductor (CMOS) process. The PA-7100 is packaged in a 504-pin ceramic pin grid array that has a copper-tungsten heat spreader.
An improved PA-7100, the PA-7150 was introduced in 1994. It operated at {{nowrap|125 MHz,}} due to improved circuit design. It was fabricated in the same CMOS26B process as the PA-7100.
Both microprocessors were fabricated at HP's Corvallis, Oregon and Fort Collins, Colorado fabrication plants.{{harvnb|DeTar|1993}}
The PA-7100LC and PA-7200 microprocessors were also based on the PA-7100.{{harnvb|Chan|Hay|Keller|Kurpanek|Schumacher|Zheng|1996}}{{harvnb|Gwennap|1994}}
Notes
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References
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- {{cite web |title=PA-7100 PA-RISC Processor |date= |publisher=OpenPA.net |url=http://www.openpa.net/pa-risc_processor_pa-7100.html}}
- {{cite journal |last1=Asprey |first1=T. |first2=G.S. |last2=Averill |first3=E. |last3=DeLano |first4=R. |last4=Mason |first5=B. |last5=Weiner |first6=J. |last6=Yetter |title=Performance features of the PA7100 microprocessor |journal=IEEE Micro |volume=13 |issue=3 |pages=22–35 |date=June 1993 |doi=10.1109/40.216746 |s2cid=27900483 |url=https://ieeexplore.ieee.org/document/216746|url-access=subscription }}
- {{cite journal |last1=Chan |first1=K.K. |last2=Hay |first2=C.C. |last3=Keller |first3=J.R. |last4=Kurpanek |first4=G.P. |last5=Schumacher |first5=F.X. |last6=Zheng |first6=J. |title=Design of the HP PA 7200 CPU |journal=Hewlett-Packard Journal |volume=47 |issue=1 |pages=25–33 |date=February 1996 |citeseerx=10.1.1.301.5229 |url=http://www.hpl.hp.com/hpjournal/96feb/feb96a3.pdf}}
- {{cite book |first1=E. |last1=DeLano |first2=W. |last2=Walker |first3=J. |last3=Yetter |first4=M. |last4=Forsyth |chapter=A high speed superscalar PA-RISC processor |chapter-url=https://ieeexplore.ieee.org/document/186696 |title=Proceedings of Compcon Spring 1992 |publisher=IEEE |date=1992 |isbn=0-8186-2655-0 |pages=116–121 |url= |doi=10.1109/CMPCON.1992.186696|s2cid=21611475 }}
- {{cite news |first=Jim |last=DeTar |title=HP spins PA-RISC architecture; part of five-year roadmap |newspaper=Electronic News |date=20 December 1993 |url=http://findarticles.com/p/articles/mi_m0EKF/is_n1994_v39/ai_15007968/}}
- {{cite news |first=Linley |last=Gwennap |title=PA-7200 Enables Inexpensive MP Systems |newspaper=Microprocessor Report |date=7 March 1994 |url=https://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/pa7200%20(mpr).pdf}}
- {{cite book |first=C. |last=Heikes |chapter=A 4.5 mm2 multiplier array for a 200 MFLOP pipelined coprocessor |chapter-url= |editor= |title=Proceedings of IEEE International Solid-State Circuits Conference — ISSCC '94 |publisher=IEEE |date=1994 |isbn=0-7803-1844-7 |pages=290–1 |url=https://ieeexplore.ieee.org/document/344637 |doi=10.1109/ISSCC.1994.344637|s2cid=56561424 }}
- {{cite book |first1=J. |last1=Yetter |first2=B. |last2=Miller |first3=W. |last3=Jaffe |first4=E. |last4=DeLano |chapter=A 100 MHz superscalar PA-RISC CPU/coprocessor chip |chapter-url=https://ieeexplore.ieee.org/document/229260 |title=1992 Symposium on VLSI Circuits Digest of Technical Papers |publisher=IEEE |date=1992 |isbn=0-7803-0701-1 |pages=12–13 |doi=10.1109/VLSIC.1992.229260|s2cid=60632513 }}
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