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PIC instruction listings

The PIC instruction set is the set of instructions that Microchip Technology PIC or dsPIC microcontroller supports. The instructions are usually programmed into the Flash memory of the processor, and automatically executed by the microcontroller on startup.

PICmicro chips have a Harvard architecture and instruction words have unusual sizes. Originally, 12-bit instructions included 5 address bits to specify the memory operand, and 9-bit branch destinations. Later revisions added opcode bits, allowing additional address bits.

They are accumulator machines, with a common accumulator "W" being one operand in all 2-operand instructions.

In the instruction set tables that follow, register numbers are referred to as "f", while constants are referred to as "k". Bit numbers (0–7) are selected by "b". Arithmetic instructions write their result to one of the inputs selected by the "d" bit: 0 indicates W, while 1 indicates that the result is written back to source register f. The C and Z status flags may be set based on the result; otherwise they are unmodified. Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag, the carry from bit 3 to bit 4, which is useful for BCD arithmetic.

Architecture

Memory operands are also referred to as "registers". Most are simply general-purpose storage (RAM), while some locations are reserved for special function registers. Except for a single accumulator (called W), almost all other registers are memory-mapped, even registers like the program counter and ALU status register. (The other exceptions, which are not memory-mapped, are the return address stack, and the tri-state registers used to configure the GPIO pins.)

Some arithmetic instructions only use one of their inputs, but still use a dbit. For example, MOVW copies the value of W to the destination. When used with d = 1, this stores W to f. There is a matching MOVF instruction which outputs the value of f. When used with d = 0, this loads f into W. When used with d = 1, the only visible effect is to set the zero flag depending on the value of f.

The instruction set does not contain conditional branch instructions. Instead, it contains conditional skip instructions which cause the following instruction to be ignored. A conditional skip followed by an unconditional branch performs a conditional branch. The skip instructions test any bit of any register. The ALU status register is one possibility.

Memory operands are specified by absolute address; the location is fixed at compile time. To provide indirect addressing, a pair of special function registers are provided:

  • The file select register (FSR) is written with the address of the desired memory operand, after which
  • The indirect file register (INDF) becomes an alias for the operand pointed to by the FSR.

This mechanism also allows up to 256 bytes of memory to be addressed, even when the instruction set only allows 5- or 7-bit absolute addresses. Models with more registers (special function registers plus RAM) than fit into the instruction provide multiple banks of memory, and use one of two mechanisms for accessing them:

  1. Most baseline core devices, and some mid-range core devices, use the high-order bits of the file select register to select the current register bank.
  2. More recent models have a separate bank select register, and a MOVLB instruction to set it.

PIC processors with more than 256 words of program use paged memory. The internal program counter and return stack are as wide as necessary to address all memory, but only the low 8 bits are visible to software in the PCL ("PC low") register. There is an additional PCLATH ("PC latch high") register which is only modified by software. Any operation which does not specify the full destination address (such as a 9-bit GOTO or an 8-bit write to the PCL register) fills in the additional high bits from the corresponding part of PCLATH. (Some PIC18 processors extend this beyond 16 bits with a PCLATU register to supply bits 16–23.)

Baseline core devices (12 bit)

This is the original 1976 instruction set, introduced in the General Instrument PIC1640 and PIC1650,{{cite book

|title=Computer Structures: Principles and Examples

|editor-first1=Daniel P. |editor-last1=Siewiorek

|editor-first2=C. Gordon |editor-last2=Bell |editor-link2=Gordon Bell

|editor-first3=Allen |editor-last3=Newell

|isbn=0-07-057302-6

|year=1982 |publisher=McGraw-Hill

|chapter=Chapter 35 PIC1650: Chip Architecture and Operation

|first=Frank M. |last=Gruppuso

|url=http://archive.computerhistory.org/resources/text/bell_gordon/bell.computer_structures_principles_and_examples.1982.102630397.pdf

|chapter-url=https://gordonbell.azurewebsites.net/tcmwebpage/computertimeline/chap35_pic1650_cs2.pdf

|access-date=2024-08-18

}} with the only additions since then being the miscellaneous instructions other than NOP.

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|+ 12-bit PIC instruction set

! 1
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0
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1
0		MnemonicC
?		Z
?		Description
colspan=16|
0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=5| opcode ||colspan=4| Miscellaneous instructions
000000000000align=left| NOPalign=left| No operation
000000000010align=left| OPTIONalign=left| Copy W to OPTION register
000000000011align=left| SLEEPalign=left| Go into standby mode
000000000100align=left| CLRWDTalign=left| Restart watchdog timer
0000000001colspan=2| falign=left| TRIS falign=left| Copy W to tri-state register (f = 1, 2 or 3)
000000010colspan=3| kalign=left| MOVLB k*align=left| Set bank select register to k
000000011110align=left| RETURN†align=left| Return from subroutine, W unmodified
000000011111align=left| RETFIE†align=left| Return from interrupt; return & enable interrupts
colspan=16|
0 || 0 ||colspan=4| opcode || d || colspan=5| register ||colspan=4| ALU operations: dest ← OP(f,W)
0000001colspan=5| falign=left| MOVWF falign=left| f ← W
000001dcolspan=5| falign=left| CLR f,dZalign=left| dest ← 0, usually written CLRW or CLRF f
000010dcolspan=5| falign=left| SUBWF f,dCZalign=left| dest ← f−W (dest ← f+~W+1)
000011dcolspan=5| falign=left| DECF f,dZalign=left| dest ← f−1
000100dcolspan=5| falign=left| IORWF f,dZalign=left| dest ← f {{pipe}} W, logical inclusive or
000101dcolspan=5| falign=left| ANDWF f,dZalign=left| dest ← f & W, logical and
000110dcolspan=5| falign=left| XORWF f,dZalign=left| dest ← f ^ W, logical exclusive or
000111dcolspan=5| falign=left| ADDWF f,dCZalign=left| dest ← f+W
001000dcolspan=5| falign=left| MOVF f,dZalign=left| dest ← f
001001dcolspan=5| falign=left| COMF f,dZalign=left| dest ← ~f, bitwise complement
001010dcolspan=5| falign=left| INCF f,dZalign=left| dest ← f+1
001011dcolspan=5| falign=left| DECFSZ f,dalign=left| dest ← f−1, then skip if zero
001100dcolspan=5| falign=left| RRF f,dCalign=left| dest ← CARRY<<7 {{pipe}} f>>1, rotate right through carry
001101dcolspan=5| falign=left| RLF f,dCalign=left| dest ← F<<1 {{pipe}} CARRY, rotate left through carry
001110dcolspan=5| falign=left| SWAPF f,dalign=left| dest ← f<<4 {{pipe}} f>>4, swap nibbles
001111dcolspan=5| falign=left| INCFSZ f,dalign=left| dest ← f+1, then skip if zero
colspan=16|
0 || 1 ||colspan=2| opc ||colspan=3| bit ||colspan=5| register ||colspan=4| Bit operations
0100colspan=3| bitcolspan=5| falign=left| BCF f,balign=left| Clear bit b of f
0101colspan=3| bitcolspan=5| falign=left| BSF f,balign=left| Set bit b of f
0110colspan=3| bitcolspan=5| falign=left| BTFSC f,balign=left| Skip if bit b of f is clear
0111colspan=3| bitcolspan=5| falign=left| BTFSS f,balign=left| Skip if bit b of f is set
colspan=16|
1 || 0 ||colspan=2| opc ||colspan=8| k ||colspan=4| Control transfers
1000colspan=8| kalign=left| RETLW kalign=left| Set W ← k, then return from subroutine
1001colspan=8| kalign=left| CALL kalign=left| Call subroutine, 8-bit address k
101colspan=9| kalign=left| GOTO kalign=left| Jump to 9-bit address k{{Cite book

|publisher=Microchip Technology

|year=2007

|url=http://ww1.microchip.com/downloads/en/DeviceDoc/41239D.pdf

|title=PIC10F200/202/204/206 Data Sheet

|page=52

|access-date=2015-01-15

|archive-url=https://web.archive.org/web/20150811030147/http://ww1.microchip.com/downloads/en/DeviceDoc/41239D.pdf

|archive-date=2015-08-11

|url-status=dead

}}

colspan=16|
1 || 1 ||colspan=2| opc ||colspan=8| 8-bit immediate ||colspan=4| Operations with W and 8-bit literal: W ← OP(k,W)
1100colspan=8| kalign=left| MOVLW kalign=left| W ← k
1101colspan=8| kalign=left| IORLW kZalign=left| W ← k {{pipe}} W, bitwise logical or
1110colspan=8| kalign=left| ANDLW kZalign=left| W ← k & W, bitwise and
1111colspan=8| kalign=left| XORLW kZalign=left| W ← k ^ W, bitwise exclusive or
colspan=16|
1
1 || 1
0 ||
9 ||
8 ||
7 ||
6 ||
5 ||
4 ||
3 ||
2 ||
1 ||
0 || Mnemonic || C
? || Z
? || Description

*: Extended instruction, not available on most 12-bit PICs. Of the models with extended RAM, most (e.g. 16C5x, 16F5x) extend the register address space using the high-order bits of the FSR. A few (e.g. PIC12F529T39A) have a separate bank select register which can be set with this instruction.

†: Extended instruction, only available on "enhanced baseline" PICs. Only the very few models (16F527, 16F570, MCV20A) with interrupt support (and a 4-level stack) include these instructions. All such models also include MOVLB.

General Instrument PIC1670 (13 bit, obsolete)

Introduced in 1979, this expanded PIC supported 64 bytes of register space (16 special function registers and 48 bytes of RAM), 1024 words of ROM, a 6-level hardware stack, and interrupt handling. The PIC1665 was a variant with external ROM used for developing firmware for the mask ROM 1670.

It added a signed overflow bit to the status register (bit 3). Status register bits 4 and 5 provided read-only access to the high 2 bits of the 10-bit program counter.

The instruction set is mostly the same as the 12-bit PIC with the address field enlarged. However, the 8-bit immediate instructions gain an additional opcode bit. Rather than adding an additional four instructions with an 8-bit immediate operand, the instruction set adds two instructions with 8-bit operands, two instructions with 7-bit operands (6-bit address plus direction bit), and four instructions with 6-bit operands (6-bit address):

  • The 8-bit immediate group grows to 6 instructions by adding ADDLW and RETLW. The latter is moved out of the control transfer group, allowing a full 10-bit address in the CALL instruction.
  • The ALU operations group gains add/subtract with carry (ADCWF, SUBBWF) instructions (7-bit operands).
  • The CLRW instruction is deleted (it wastes a 6-bit memory address and duplicates MOVLW 0).
  • Five new instructions with a 6-bit memory address operands are added. These do not have a destination select bit, and include three "compare and skip" instructions which do not write a result, and two "rotate without carry" instructions.

This instruction set is not used in any currently manufactured part and is of historical interest only.

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|+ 13-bit PIC1670 instruction set (obsolete){{cite tech report

|type=Data Sheet

|title=PIC1670 8-bit Microcomputer

|author=General Instrument

|url=http://www.t-es-t.hu/download/microchip/gi_pic1670.pdf

|access-date=2024-08-18

}}

! 1
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0		MnemonicC
?		Z
?		Description
colspan=17|
0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=6| opcode ||colspan=4| Miscellaneous instructions
0000000000000align=left| NOPalign=left| No operation
0000000000001align=left| HALTalign=left| Halt processor (PIC1665 only)
0000000000010align=left| RETFIalign=left| Return from interrupt
0000000000011align=left| RETFSalign=left| Return from subroutine, W unmodified
0000000000100align=left| DAWalign=left| Decimal Adjust W
colspan=17|
0 || 0 ||colspan=4| opcode || d ||colspan=6| register ||colspan=4| ALU operations same as 12- and 14-bit PIC except
000001dcolspan=6| falign=left| SUBBWF f,dCZalign=left| dest ← f−W−{{overline|C}} = f+~W+C (not {{s|CLR f,d}})
001000dcolspan=6| falign=left| ADCWF f,dCZalign=left| dest ← f+W+C (not {{s|MOVF f,d}})
colspan=17|
0 || 1 ||colspan=2| opc ||colspan=3| bit ||colspan=6| register ||colspan=4| Bit operations same as 12- and 14-bit PIC
colspan=17|
1 || 0 || 0 || 0 ||colspan=3| opcode ||colspan=6| register ||colspan=4| Additional ALU operations, no choice of destination
1000000colspan=6| falign=left| MOVFW fZalign=left| W ← f (= MOVF f,0)
1000001colspan=6| falign=left| CLRF fZalign=left| f ← 0 (for CLRW, use MOVLW 0)
1000010colspan=6| falign=left| RRNC falign=left| f ← f<<7 {{pipe}} f>>1, rotate right no carry
1000011colspan=6| falign=left| RLNC falign=left| f ← f<<1 {{pipe}} f>>7, rotate left no carry
1000100colspan=6| falign=left| CPFSLT falign=left| Compare and skip if f < W (unsigned)
1000101colspan=6| falign=left| CPFSEQ falign=left| Compare and skip if f = W
1000110colspan=6| falign=left| CPFSGT falign=left| Compare and skip if f > W (unsigned)
1000111colspan=6| falign=left| TESTF fZalign=left| f ← f (= MOVF f,1)
colspan=17|
1 || 0 ||colspan=3| opcode ||colspan=8| 8-bit immediate ||colspan=4| Operations with W and 8-bit literal: W ← OP(k,W)
10010colspan=8| kalign=left| MOVLW kalign=left| W ← k
10011colspan=8| kalign=left| ADDLW kCZalign=left| W ← k+W
10100colspan=8| kalign=left| IORLW kZalign=left| W ← k {{pipe}} W, bitwise logical or
10101colspan=8| kalign=left| ANDLW kZalign=left| W ← k & W, bitwise and
10110colspan=8| kalign=left| XORLW kZalign=left| W ← k ^ W, bitwise exclusive or
10111colspan=8| kalign=left| RETLW kalign=left| W ← k, then return from subroutine
colspan=17|
1 || 1 || c ||colspan=10| k ||colspan=4| Control transfers
110colspan=10| kalign=left| GOTO kalign=left| Jump to address k
111colspan=10| kalign=left| CALL kalign=left| Call subroutine
colspan=17|
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1 || 1
0 ||
9 ||
8 ||
7 ||
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5 ||
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3 ||
2 ||
1 ||
0 || Mnemonic || C
? || Z
? || Description

Mid-range core devices (14 bit)

These devices feature a 14-bit wide code memory, and an improved 8 level deep call stack. The instruction set differs very little from the baseline devices, but the 2 additional opcode bits allow 128 registers and 2048 words of code to be directly addressed. There are a few additional miscellaneous instructions, and two additional 8-bit literal instructions, add and subtract. The mid-range core is available in the majority of devices labeled PIC12 and PIC16.

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|+ 14-bit PIC instruction set

! 1
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0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=7| opcode ||colspan=4| Miscellaneous instructions
00000000000000align=left| NOPalign=left| No operation
00000000001000align=left| RETURNalign=left| Return from subroutine, W unmodified
00000000001001align=left| RETFIEalign=left| Return from interrupt
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| 0

0000001100010align=left| OPTIONalign=left| Copy W to OPTION register (deprecated)
00000001100011align=left| SLEEPalign=left| Go into standby mode
00000001100100align=left| CLRWDTalign=left| Restart watchdog timer
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| 0

00000011001colspan=2| falign=left| TRIS falign=left| Copy W to tri-state register (f = 1, 2 or 3) (deprecated)
colspan=18|
0 || 0 ||colspan=4| opcode || d ||colspan=7| register ||colspan=4| ALU operations: dest ← OP(f,W)
0000001colspan=7| falign=left| MOVWF falign=left| f ← W
000001dcolspan=7| falign=left| CLR f,dZalign=left| dest ← 0, usually written CLRW or CLRF f
000010dcolspan=7| falign=left| SUBWF f,dCZalign=left| dest ← f−W (dest ← f+~W+1)
000011dcolspan=7| falign=left| DECF f,dZalign=left| dest ← f−1
000100dcolspan=7| falign=left| IORWF f,dZalign=left| dest ← f {{pipe}} W, logical inclusive or
000101dcolspan=7| falign=left| ANDWF f,dZalign=left| dest ← f & W, logical and
000110dcolspan=7| falign=left| XORWF f,dZalign=left| dest ← f ^ W, logical exclusive or
000111dcolspan=7| falign=left| ADDWF f,dCZalign=left| dest ← f+W
001000dcolspan=7| falign=left| MOVF f,dZalign=left| dest ← f
001001dcolspan=7| falign=left| COMF f,dZalign=left| dest ← ~f, bitwise complement
001010dcolspan=7| falign=left| INCF f,dZalign=left| dest ← f+1
001011dcolspan=7| falign=left| DECFSZ f,dalign=left| dest ← f−1, then skip if zero
001100dcolspan=7| falign=left| RRF f,dCalign=left| dest ← CARRY<<7 {{pipe}} f>>1, rotate right through carry
001101dcolspan=7| falign=left| RLF f,dCalign=left| dest ← f<<1 {{pipe}} CARRY, rotate left through carry
001110dcolspan=7| falign=left| SWAPF f,dalign=left| dest ← f<<4 {{pipe}} f>>4, swap nibbles
001111dcolspan=7| falign=left| INCFSZ f,dalign=left| dest ← f+1, then skip if zero
colspan=18|
0 || 1 ||colspan=2| opc ||colspan=3| bit ||colspan=7| register ||colspan=4| Bit operations
0100colspan=3| bitcolspan=7| falign=left| BCF f,balign=left| Clear bit b of f
0101colspan=3| bitcolspan=7| falign=left| BSF f,balign=left| Set bit b of f
0110colspan=3| bitcolspan=7| falign=left| BTFSC f,balign=left| Skip if bit b of f is clear
0111colspan=3| bitcolspan=7| falign=left| BTFSS f,balign=left| Skip if bit b of f is set
colspan=18|
1 || 0 || c ||colspan=11| k ||colspan=4| Control transfers
100colspan=11| kalign=left| CALL kalign=left| Call subroutine
101colspan=11| kalign=left| GOTO kalign=left| Jump to address k
colspan=18|
1 || 1 ||colspan=4| opcode ||colspan=8| 8-bit immediate ||colspan=4| Operations with W and 8-bit literal: W ← OP(k,W)
1100style="background:lightgrey;"| xstyle="background:lightgrey;"| xcolspan=8| kalign=left| MOVLW kalign=left| W ← k
1101style="background:lightgrey;"| xstyle="background:lightgrey;"| xcolspan=8| kalign=left| RETLW kalign=left| W ← k, then return from subroutine
111000colspan=8| kalign=left| IORLW kZalign=left| W ← k {{pipe}} W, bitwise logical or
111001colspan=8| kalign=left| ANDLW kZalign=left| W ← k & W, bitwise and
111010colspan=8| kalign=left| XORLW kZalign=left| W ← k ^ W, bitwise exclusive or
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| 1

11011colspan=8| kstyle="text-align:left;" colspan="4"| (reserved)
11110style="background:lightgrey;"| xcolspan=8| kalign=left| SUBLW kCZalign=left| W ← k−W (dest ← k+~W+1)
11111style="background:lightgrey;"| xcolspan=8| kalign=left| ADDLW kCZalign=left| W ← k+W
colspan=18|
1
3 || 1
2 || 1
1 || 1
0 ||
9 ||
8 ||
7 ||
6 ||
5 ||
4 ||
3 ||
2 ||
1 ||
0 || Mnemonic || C
? || Z
? || Description

Enhanced mid-range core devices (14 bit)

Enhanced mid-range core devices introduce a deeper hardware stack, additional reset methods, 14 additional instructions and C programming language optimizations.{{cite web|title=Introducing the Enhanced Mid-Range Architecture|url=https://web.archive.org/web/20220418040755/http://www.microchip.com/stellent/groups/SiteComm_sg/documents/DeviceDoc/en542713.pdf|website=Microchip}} In particular. there are two INDF registers (INDF0 and INDF1), and two corresponding FSR register pairs (FSRnL and FSRnH). Special instructions use FSRn registers like address registers, with a variety of addressing modes.

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|+ 14-bit enhanced PIC additional instructions

! 1
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colspan=18|
0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=7| opcode ||colspan=4| Miscellaneous instructions
00000000000001align=left| RESETalign=left| Software reset
00000000001010align=left| CALLWalign=left| Push PC, then jump to PCLATH:W
00000000001011align=left| BRWalign=left| PC ← PC + W, relative jump using W
00000000010n00align=left| MOVIW ++FSRnZalign=left| Increment FSRn, then W ← INDFn
00000000010n01align=left| MOVIW −−FSRnZalign=left| Decrement FSRn, then W ← INDFn
00000000010n10align=left| MOVIW FSRn++Zalign=left| W ← INDFn, then increment FSRn
00000000010n11align=left| MOVIW FSRn−−Zalign=left| W ← INDFn, then decrement FSRn
00000000011ncolspan=2| malign=left| MOVWI using FSRnalign=left| INDFn ← W, same modes as MOVIW
000000001colspan=5| kalign=left| MOVLB kalign=left| BSR ← k, move literal to bank select register
colspan=18|
1 || 1 ||colspan=4| opcode || d ||colspan=7| register ||colspan=4| ALU operations: dest ← OP(f,W)
110101dcolspan=7| falign=left| LSLF f,dCZalign=left| dest ← f << 1, logical shift left
110110dcolspan=7| falign=left| LSRF f,dCZalign=left| dest ← f >> 1, logical shift right
110111dcolspan=7| falign=left| ASRF f,dCZalign=left| dest ← f >> 1, arithmetic shift right
111011dcolspan=7| falign=left| SUBWFB f,dCZalign=left| dest ← f + ~W + C, subtract with carry
111101dcolspan=7| falign=left| ADDWFC f,dCZalign=left| dest ← f + W + C, add with carry
colspan=18|
1 || 1 ||colspan=5| opcode ||colspan=7| k ||colspan=4| Operations with literal k
1100010ncolspan=6| kalign=left| ADDFSR FSRn,kalign=left| FSRn ← FSRn + k, add 6-bit signed offset
1100011colspan=7| kalign=left| MOVLP kalign=left| PCLATH ← k, move 7-bit literal to PC latch high
11001colspan=9| kalign=left| BRA kalign=left| PC ← PC + k, branch relative using 9-bit signed offset
1111110ncolspan=6| kalign=left| MOVIW k[FSRn]Zalign=left| W ← [FSRn+k], 6-bit signed offset
1111111ncolspan=6| kalign=left| MOVWI k[FSRn]align=left| [FSRn+k] ← W, 6-bit signed offset
colspan=18|
1
3 || 1
2 || 1
1 || 1
0 ||
9 ||
8 ||
7 ||
6 ||
5 ||
4 ||
3 ||
2 ||
1 ||
0 || Mnemonic || C
? || Z
? || Description

ELAN Microelectronics clones (13 or 15 bit)

ELAN Microelectronics Corp. make a series of PICmicro-like microcontrollers with a 13-bit instruction word.{{Cite web|url=http://www.emc.com.tw/eng/products.asp|title = 義隆電子股份有限公司義隆電子，再創未來！}} The instructions are mostly compatible with the mid-range 14-bit instruction set, but limited to a 6-bit register address (16 special-purpose registers and 48 bytes of RAM) and a 10-bit (1024 word) program space.

The 10-bit program counter is accessible as R2. Reads access only the low bits, and writes clear the high bits. An exception is the TBL instruction, which modifies the low byte while preserving bits 8 and 9.

The 7 accumulator-immediate instructions are renumbered relative to the 14-bit PICmicro, to fit into 3 opcode bits rather than 4, but they are all there, as well as an additional software interrupt instruction.

There are a few additional miscellaneous instructions, and there are some changes to the terminology (the PICmicro OPTION register is called the CONTrol register; the PICmicro TRIS registers 1–3 are called I/O control registers 5–7), but the equivalents are obvious.

class="wikitable" style="text-align:center"

|+ 13-bit EM78 instruction set{{Citation |url=https://www.emc.com.tw/upload/2019_07_232/EM78xxx13-bit%20Instruction%20Set_20110324.pdf |title=M78XXX 13-Bit Instruction Set |type=Application Note |id=AN EM78xxx-20110309 |date=2011-03-09 |author=ELAN Microelectronics Corp. |access-date=2025-01-11}}{{Citation |url=http://www.emc.com.tw/upload/2019_01_15(0_0)b2/EM78P157N.pdf#page=36 |title=EM78P157N 8-bit microcontroller with OTP ROM Product Specification |version=version 1.3 |date=26 April 2016 |author=ELAN Microelectronics Corp. |access-date=2020-06-06 |archive-url=https://web.archive.org/web/20160304054645/http://www.emc.com.tw/eng/database/Data_Sheet/8BIT/EM78P157N.pdf#page=36 |archive-date=2016-03-04 |url-status=live}}{{Citation |url=http://www.emc.com.tw/upload/2019_01_15(0_0)b2/EM78P143.pdf#page=83 |title=EM78P143 8-bit microprocessor with OTP ROM Product Specification |version=version 1.7 |date=25 April 2016 |author=ELAN Microelectronics Corp. |access-date=2020-06-06 |page=77}}

! 1
2

1
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0
9
8
7
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5
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3
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1
0		MnemonicC
?		Z
?		Description
colspan=17|
0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=6| opcode ||colspan=4| Miscellaneous instructions
0000000000000align=left| NOP*align=left| No operation
0000000000001align=left| DAA†Calign=left| Decimal Adjust after Addition
0000000000010align=left| CONTW*align=left| Write CONT register (CONT ← W)
0000000000011align=left| SLEP*align=left| Go into standby mode (WDT ← 0, stop clock)
0000000000100align=left| WDTC*align=left| Restart watchdog timer (WDT ← 0)
000000000colspan=4| falign=left| IOW f{{primef|c=†}}align=left| Copy W to I/O control register (f = 5–7, 11–15)
0000000010000align=left| ENI†align=left| Enable interrupts
0000000010001align=left| DISI†align=left| Disable interrupts
0000000010010align=left| RETalign=left| Return from subroutine, W unmodified
0000000010011align=left| RETIalign=left| Return from interrupt; return & enable interrupts
0000000010100align=left| CONTR†align=left| Read CONT register (W ← CONT)
000000001colspan=4| falign=left| IOR f{{primef|c=†}}align=left| Copy I/O control register to W (f = 5–7, 11–15)
0000000100000align=left| TBL†CZalign=left| PCL += W, preserve PC bits 8 & 9
0000010000001align=left| TBWR†‡align=left| Start flash write
colspan=17|
0 || 0 ||colspan=4| opcode || d ||colspan=6| register ||colspan=4| ALU operations same as 12- and 14-bit PIC
0 || 1 ||colspan=2| opc ||colspan=3| bit ||colspan=6| register ||colspan=4| Bit operations same as 12- and 14-bit PIC
1 || 0 || c ||colspan=10| k ||colspan=4| Control transfers same as 14-bit PIC
colspan=17|
1 || 1 ||colspan=3| opcode ||colspan=8| 8-bit immediate ||colspan=4| Operations with W and 8-bit literal: W ← OP(k,W)
110colspan=2| opcolspan=8| kcolspan=4| MOV/IOR/AND/XOR, same as 12-bit PIC
11100colspan=8| kalign=left| RETLW kalign=left| W ← k, then return from subroutine
11101colspan=8| kalign=left| SUBLW kCZalign=left| W ← k−W (W ← k+~W+1)
111100colspan=7| kalign=left| INT k†align=left| Push PC, PC ← k (software interrupt, usually k=1)
11111colspan=8| kalign=left| ADDLW kCZalign=left| W ← k+W
colspan=17|
1 || 1 || 1 || 1 || 0 || 1 ||colspan=3| opcode ||colspan=4| k ||colspan=4| Extensions (replacing INT k for k≥128 on later models){{r|EM78P143}}{{Citation |url=http://www.emc.com.tw/Twn/database/Data_Sheet/8BIT/EM78P346N.pdf#page=85 |title=EM78P346N 8-bit microprocessor with OTP ROM Product Specification |version=version 1.5 |date=April 2016 |author=ELAN Microelectronics Corp. |access-date=2019-07-11 |page=77}}{{Citation |url=http://www.emc.com.tw/twn/database/Data_Sheet/COM/EM78860.pdf#page=17 |title=EM78860 8-bit Micro-controller |date=17 April 2000 |author=ELAN Microelectronics Corp. |access-date=2019-07-11 |page=17}}
111101000colspan=4| kalign=left| PAGE kalign=left| Select ROM page k (like MOVLP k)
111101001colspan=4| kalign=left| BANK k†align=left| Select RAM bank k
111101010colspan=4| kalign=left| LCALL k†align=left| Long call with 17-bit address (2-word instruction)
111101011colspan=4| kalign=left| LJMP k†align=left| Long jump with 17-bit address (2-word instruction)
1111011colspan=6| falign=left| TBRD f{{primef|c=†}}align=left| Read ROM at TBHP:TBLP into specified register
colspan=17|
1
2 || 1
1 || 1
0 ||
9 ||
8 ||
7 ||
6 ||
5 ||
4 ||
3 ||
2 ||
1 ||
0 || Mnemonic || C
? || Z
? || Description

*: Same opcode as 12-bit PIC

†: Instruction unique to EM78 instruction set with no PIC equivalent

‡: Only on flash memory models (EM78F724N)

Some models support multiple ROM, RAM, or special-purpose register banks, in a manner similar to other PIC microcontrollers. Special-purpose registers 0x5–0xF and RAM locations 0x20–0x3F each have their own bank select bits. Registers 0x0–0x4 (including the bank select register 0x1) and RAM locations 0x10–0x1F are global.

There is also a 15-bit variant of the instruction set, which is almost identical except that the register numbers are enlarged to 8 bits and the call and jump addresses are enlarged to 12 bits. Other differences:{{Citation |url=http://www.emc.com.tw/twn/database/Data_Sheet/8BIT/EM78F641N.pdf#page=174 |title=EM78F648/644/642/641N/548/544/542/541N Flash Series 8-Bit Microcontroller Product Specification |version=version 1.2 |date=15 March 2013 |author=ELAN Microelectronics Corp. |access-date=2019-07-11 |pages=162–165}}

  • The CONTW, IOW, CONTR, IOR and INT instructions are deleted,
  • Operations with an 8-bit literal have two 0 bits added as bits 8 and 9,
  • Extensions with a 4-bit literal have two 0 bits added as bits 4 and 5,
  • The PAGE and BANK instructions are renamed SBANK and GBANK and perform bank switching on special-purpose registers and the banked portion of general-purpose RAM respectively.

A second generation 15-bit instruction set expands the address space to:

  • 80 device control registers (all except the first 5 banked),
  • 48 bytes of unbanked RAM (0x50–0x7F), and
  • 128 bytes of banked RAM (0x80–0xFF),

These also include several additional instructions:

class="wikitable" style="text-align:center"

|+ 15-bit EM78/EM88 instruction set extensionsDerived from instruction encoding tables in Elan [http://www.emc.com.tw/eng/database/Sa2/Gp/Dt/eUIDEII_v2.19.60.14.rar eUIDE II v2.19.60.14], released 2019-05-01, accessed 2019-07-13. Specifically the Bin/*.cfg files.{{Citation |url=https://www.emc.com.tw/upload/2019_07_232/EM78xxx15-bit%20Instruction%20Set%20_20140114_.pdf |title=EM78XXX 15-Bit Instruction Set |type=Application Note |id=AN EM78xxx-20140114 |date=2014-01-14 |author=ELAN Microelectronics Corp. |access-date=2025-01-11}}

! 1
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1
3		1
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0		MnemonicC
?		Z
?		Description
colspan=19|
0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=7| opcode ||colspan=4| Miscellaneous instructions
000000000000000align=left| NOP*align=left| No operation
000000000000001align=left| DAA*Calign=left| Decimal Adjust after Addition
000000000000011align=left| SLEP*align=left| Go into standby mode (WDT ← 0, stop clock)
000000000000100align=left| WDTC*align=left| Restart watchdog timer (WDT ← 0)
000000000000101align=left| MULW†align=left| 8×8 → 16-bit multiply
000000000000110align=left| DIVW†align=left| 8÷8 → 8,8-bit divide
000000000010000align=left| ENI*align=left| Enable interrupts
000000000010001align=left| DISI*align=left| Disable interrupts
000000000010010align=left| RET*align=left| Return from subroutine, W unmodified
000000000010011align=left| RETI*align=left| Return from interrupt; return & enable interrupts
000000000010110align=left| RESETalign=left| Software reset
000000000010111align=left| TBWRalign=left| Flash ROM write
000000001colspan=6| kalign=left| INT kalign=left| Software interrupt at address 2×k
00000001colspan=3| bitcolspan=4| falign=left| BTG f,balign=left| Invert (toggle) bit b of f (limited address range)
colspan=19|
0 || 0 ||colspan=4| opcode || d ||colspan=8| register ||colspan=4| ALU operations same as EM78 and PIC
0 || 1 ||colspan=2| opc ||colspan=3| bit ||colspan=8| register ||colspan=4| Bit operations same as EM78 and PIC
1 || 0 || c ||colspan=12| k ||colspan=4| Control transfers same as EM78 and 14-bit PIC
colspan=19|
1 || 1 ||colspan=3| opcode || 0 || 0 ||colspan=8| 8-bit immediate ||colspan=4| Operations with 8-bit literal same as EM78 (except INT)
1 || 1 ||colspan=5| opcode ||colspan=8| register or immediate ||colspan=4| Instruction set extensions
1100001colspan=8| falign=left| JE ralign=left| Skip if W = f
1100010colspan=8| falign=left| JGE ralign=left| Skip if W > f
1100011colspan=8| falign=left| JLE ralign=left| Skip if W < f
1100101colspan=8| kalign=left| JE kalign=left| Skip if W = k
bgcolor=lightgrey

| 1

100110colspan=8| kalign=left colspan=4| (reserved)
1100111colspan=8| falign=left| TBRDA falign=left| Read ROM at TBHP:TBLP into f; msbits into W
1101001colspan=8| kalign=left| SJC addressalign=left| Jump to PC + sext(k) if carry set
1101010colspan=8| kalign=left| SJNC addressalign=left| Jump to PC + sext(k) if carry clear
1101011colspan=8| kalign=left| SJZ addressalign=left| Jump to PC + sext(k) if zero flag set
1101101colspan=8| kalign=left| SJNZ addressalign=left| Jump to PC + sext(k) if zero flag clear
110111dcolspan=8| falign=left| RRA/RR falign=left| dest ← f<<7 | f>>1, rotate right without carry
1110001colspan=8| falign=left| XCH falign=left| Exchange f ↔ W
111001dcolspan=8| falign=left| RLA/RL falign=left| dest ← f<<1 | f>>7, rotate left without carry
1110101colspan=8| falign=left| MUL f{{primef|c=‡}}align=left| PRODH:PRODL ← f × W
bgcolor=lightgrey

| 1

11011xcolspan=8| kcolspan=4 align=left| (reserved)
111100dcolspan=8| falign=left| SUBBCZalign=left| dest ← f + ~W + C, subtract with carry
11110100000colspan=4| kalign=left| SBANK k*align=left| Select special function register bank k
11110100100colspan=4| kalign=left| GBANK k*align=left| Select RAM bank k
11110101000colspan=4| kalign=left| LCALL k*align=left| Long call with 19-bit address (2-word instruction)
11110101100colspan=4| kalign=left| LJMP k*align=left| Long jump with 19-bit address (2-word instruction)
1111011colspan=8| falign=left| TBRD f{{primef|c=*}}align=left| Read ROM at TBHP:TBLP into f
1111101colspan=8| falign=left| NEG fCZalign=left| f ← −f (f ← ~f + 1), negate
111111dcolspan=8| falign=left| ADC fCZalign=left| dest ← f + W + C, add with carry

*: Same opcode as 13-bit EM78

†: Only on EM89F768N; operands and results in special registers

‡: Only on EM88F794N, MTF213 and MTF351

Holtek clones (14, 15 or 16 bit)

Holtek make numerous 8-bit microcontrollers with a 14-bit instruction word equivalent to the (non-enhanced) mid-range core. The instruction encodings all fit into 14 bits and provide 7-bit operand addresses.

The instruction format is identical to Microchip's, but the opcodes are assigned in a different order, and the manufacturer uses different instruction mnemonics. The accumulator is called ACC rather than W, and the destination is specified by a suffix to the instruction mnemonic rather than an operand. (Instructions which do not use the accumulator by default write back to memory, and use an A suffix to indicate the destination is the accumulator. Two-operand instructions by default write to the accumulator, and use an M suffix to indicate a memory destination.)

In addition to the different opcode assignment, there are semantic differences in a few instructions:

  • The subtract instructions subtract the operand from the accumulator, while Microchip's subtract instructions do the reverse. (This makes the subtract immediate instruction redundant, as it is equivalent to an add of the negative.)
  • The move-to-accumulator and clear instructions do not modify any flags.
  • In addition to the zero, carry, and digit carry flags (called AC by Holtek), there an overflow flag which is set by the same add and subtract instructions which set AC.

Several operations have been added to the 14-bit PICmicro repertoire:

  • Rotate one bit left and right without carry,
  • Set operand to all-ones,
  • Skip if operand is zero (without incrementing or decrementing it first),
  • Skip if operand is non-zero (some models),
  • Add and subtract with carry,
  • Decimal adjust after addition, for binary-coded decimal arithmetic, and
  • Read from program ROM, for table lookup. This uses TBHP and TBLP registers as a 16-bit pointer, fetches the word there, and stores the low byte in a specified location. The high 6–8 bits of the fetched word are stored in the TBLH register. A second form uses only TBLP and reads from the highest 256-byte page in ROM. Some models include a variant which pre-increments TBLP.
  • Most models support a second instruction to reset the watchdog timer, which must alternate with the first; repetitions of one instruction are ignored. This permits two independent watchdog routines to run, and failure of either will trigger the watchdog.
  • Holtek provide two indirect addressing registers, like the enhanced 14-bit PIC. Some models (e.g. HT66F70A) provide three. The first indirect addressing register (IAR0) uses an 8-bit address register (MP0), and always addresses the low bank of RAM. IAR1 and IAR2 provide additional RAM address bits (MP1H and MP2H) and allow access to additional banks of RAM.{{Citation |url=https://www.holtek.com.tw/webapi/116745/an0407e.pdf |title=HT8 MCU Extended Instruction Set Applications |type=Application Note |id=AN0407E |date=11 December 2016 |author=Holtek Semiconductor Inc. |access-date=2024-02-09}}

15-bit models use bit 14 of the instruction as an 8th operand address bit and a 12th CALL/JMP target address bit. 16-bit models add a 13th CALL/JMP target address bit, but do not add a 9th operand addresses bit.{{Citation |url=https://buybestelectronic.com/part-image/7300/datasheet/7300.pdf#page=32 |title=2.4GHz 8-Bit Flash RF TX/RX MCU BC66F840/BC66F850/BC66F860 |type=Data sheet |version=version 1.60 |page=32 |date=26 November 2019 |author=Holtek Semiconductor Inc. |access-date=2024-02-09 |postscript=.}} Note that operand addresses only go to 0xFF, with additional RAM addressed by banking.

Instead, some 16-bit models support an extended instruction set. This adds a few new instructions (skip on byte without inc/decrement, subtract immediate with carry, ROM read with address increment), but also adds 2-word "long" variants of all memory instructions. When bit 15 of the opcode is set, it indicates that the 8-bit operand address in opcode bits 0–6 and 14 is extended to 16 bits using bits 0–7 of the following instruction word. Such instructions are written with an L prefix (LADD vs. ADD) and take an extra cycle to execute.

class="wikitable" style="text-align:center"

|+ 14-bit Holtek instruction set{{cite web |title=Mouse Adventures #3: Writing a Disassembler |first=Ash "Ninji" |last=Wolf |date=12 December 2018 |access-date=8 July 2019 |url=https://wuffs.org/blog/mouse-adventures-part-3}}

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equivalent		C
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colspan=19|
0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=3| opcode ||colspan=5| Miscellaneous instructions
00000000000000align=left| NOPalign=left| NOPalign=left| No operation
00000000000001align=left| CLR WDT1align=left| CLRWDTalign=left| Restart watchdog timer
00000000000010align=left| HALTalign=left| SLEEPalign=left| Go into low-power mode
00000000000011align=left| RETalign=left| RETURNalign=left| Return from subroutine
00000000000100align=left| RETIalign=left| RETFIEalign=left| Return from interrupt
00000000000101align=left| CLR WDT2bgcolor=lightgrey align=left| ≈CLRWDTalign=left| Restart watchdog timer
style="background:lightgrey;"

| 0

000000000011xstyle="text-align:left;" colspan="5"| (reserved)
style="background:lightgrey;"

| 0

000000colspan=4| ≠0xxxstyle="text-align:left;" colspan="5"| (reserved)
colspan=19|
0 || 0 || 0 ||colspan=3| opcode || d ||colspan=7| address ||colspan=5| ALU operations part 1: dest ← OP(ACC,[m])*
0000001colspan=7| malign=left| MOV [m],Aalign=left| MOVWF malign=left| [m] ← ACC
000001dcolspan=7| malign=left| CPLA/CPL [m]align=left| COMF m,dZalign=left| dest ← ~[m], bitwise complement
000010dcolspan=7| malign=left| {{nobr|SUB/SUBM A,[m]}}bgcolor=lightgrey align=left| ≠SUBWF m,dCZalign=left| dest ← ACC − [m] (dest ← ACC+~[m]+1)
000011dcolspan=7| malign=left| ADD/ADDM A,[m]align=left| ADDWF m,dCZalign=left| dest ← ACC + [m]
000100dcolspan=7| malign=left| XOR/XORM [m]align=left| XORWF m,dZalign=left| dest ← ACC ^ [m], logical exclusive or
000101dcolspan=7| malign=left| OR/ORM [m]align=left| IORWF m,dZalign=left| dest ← ACC {{!}} [m], logical inclusive or
000110dcolspan=7| malign=left| AND/ANDM [m]align=left| ANDWF m,dZalign=left| dest ← ACC & [m], logical and
0001110colspan=7| malign=left| MOV A,[m]bgcolor=lightgrey align=left| ≈MOVF m,0align=left| ACC ← [m]
style="background:lightgrey;"

| 0

001111colspan=7| m—align=left| ≈MOVF m,1align=left| [m] ← [m]
colspan=19|
0 || 0 || 1 ||colspan=3| opcode ||colspan=8| 8-bit immediate ||colspan=5| Operations with 8-bit literal: ACC ← OP(ACC,k)
001000colspan=8| kalign=left| SBC A,k†bgcolor=lightgrey| —CZalign=left| ACC ← ACC + ~[m] + C, subtract with carry
001001colspan=8| kalign=left| RET A,kalign=left| RETLW kalign=left| ACC ← k, then return from subroutine
001010colspan=8| kalign=left| SUB A,kbgcolor=lightgrey align=left| ≠SUBLW kCZalign=left| ACC ← ACC − k (ACC ← ACC+~k+1)
001011colspan=8| kalign=left| ADD A,kalign=left| ADDLW kCZalign=left| ACC ← ACC + k
001100colspan=8| kalign=left| XOR A,kalign=left| XORLW kZalign=left| ACC ← ACC ^ k, logical exclusive or
001101colspan=8| kalign=left| OR A,kalign=left| IORLW kZalign=left| ACC ← ACC {{!}} k, logical inclusive or
001110colspan=8| kalign=left| AND A,kalign=left| ANDLW kZalign=left| ACC ← ACC & k, logical and
001111colspan=8| kalign=left| MOV A,kalign=left| MOVLW kalign=left| ACC ← k
colspan=19|
0 || 1 ||colspan=4| opcode || d ||colspan=7| address ||colspan=5| ALU operations part 2: dest ← OP(ACC,[m])*
010000dcolspan=7| malign=left| SZA/SZ [m]bgcolor=lightgrey| —align=left| dest ← [m], skip next instruction if zero
010001dcolspan=7| malign=left| {{nobr|SWAPA/SWAP [m]}}align=left| SWAPF m,dalign=left| dest ← [m]<<4 {{!}} [m]>>4, swap nibbles
010010dcolspan=7| malign=left| SBC/SBCM A,[m]bgcolor=lightgrey align=left| ≠SUBWFB m,dCZalign=left| dest ← ACC + ~[m] + C, subtract with carry
010011dcolspan=7| malign=left| ADC/ADCM A,[m]align=left| ADDWFC m,dCZalign=left| dest ← ACC + [m] + C, add with carry
010100dcolspan=7| malign=left| INCA/INC [m]align=left| INCF m,dZalign=left| dest ← [m] + 1
010101dcolspan=7| malign=left| DECA/DEC [m]align=left| DECF m,dZalign=left| dest ← [m] − 1
010110dcolspan=7| malign=left| SIZA/SIZ [m]align=left| INCFSZ m,dalign=left| dest ← [m] + 1, then skip if zero
010111dcolspan=7| malign=left| SDZA/SDZ [m]align=left| DECFSZ m,dalign=left| dest ← [m] − 1, then skip if zero
011000dcolspan=7| malign=left| RLA/RL [m]bgcolor=lightgrey| —align=left| dest ← [m] << 1 {{!}} [m] >> 7, rotate left 1 bit
011001dcolspan=7| malign=left| RRA/RR [m]bgcolor=lightgrey| —align=left| dest ← [m] << 7 {{!}} [m] >> 1, rotate right 1 bit
011010dcolspan=7| malign=left| RLCA/RLC [m]align=left| RLF m,dCalign=left| dest ← [m] << 1 {{!}} C, rotate left through carry
011011dcolspan=7| malign=left| RRCA/RRC [m]align=left| RRF m,dCalign=left| dest ← C << 7 {{!}} [m] >> 1, rotate right through carry
colspan=19|
0 || 1 || 1 || 1 ||colspan=3| opcode ||colspan=7| address ||colspan=5| Special operations: [m] ← special*
0111000colspan=7| malign=left| ITABRD [m]†bgcolor=lightgrey| —align=left| TBLH:[m] ← ROM[TBHP:++TBLP], with pre-increment
0111001colspan=7| malign=left| ITABRDL [m]†bgcolor=lightgrey| —align=left| TBLH:[m] ← ROM[0xff:++TBLP], with pre-increment
0111010colspan=7| malign=left| TABRD [m]bgcolor=lightgrey| —align=left| TBLH:[m] ← ROM[TBHP:TBLP], table lookup
0111011colspan=7| malign=left| TABRDL [m]bgcolor=lightgrey| —align=left| TBLH:[m] ← ROM[0xff:TBLP], read from last page of ROM
0111100colspan=7| malign=left| SNZ [m]†bgcolor=lightgrey| —align=left| [m] ← [m], skip next instruction if non-zero
0111101colspan=7| malign=left| DAA [m]bgcolor=lightgrey| —Calign=left| [m] ← DAA(ACC), decimal adjust after BCD addition
0111110colspan=7| malign=left| CLR [m]bgcolor=lightgrey align=left| ≈CLRF malign=left| [m] ← 0
0111111colspan=7| malign=left| SET [m]bgcolor=lightgrey| —align=left| [m] ← 255
colspan=19|
1 || 0 || c ||colspan=11| k ||colspan=5| Control transfers
100colspan=11| kalign=left| CALL kalign=left| CALL kalign=left| Call subroutine
101colspan=11| kalign=left| JMP kalign=left| GOTO kalign=left| Jump to address k
colspan=19|
1 || 1 ||colspan=2| opc ||colspan=3| bit ||colspan=7| address ||colspan=5| Bit operations*
1100colspan=3| bitcolspan=7| malign=left| SET [m].balign=left| BSF m,balign=left| Set bit b of [m]
1101colspan=3| bitcolspan=7| malign=left| CLR [m].balign=left| BCF m,balign=left| Clear bit b of [m]
1110colspan=3| bitcolspan=7| malign=left| SNZ [m].balign=left| BTFSS m,balign=left| Skip if bit b of [m] is set
1111colspan=3| bitcolspan=7| malign=left| SZ [m].balign=left| BTFSC m,balign=left| Skip if bit b of [m] is clear
colspan=19|
1
3 || 1
2 || 1
1 || 1
0 ||
9 ||
8 ||
7 ||
6 ||
5 ||
4 ||
3 ||
2 ||
1 ||
0 || Mnemonic || PIC
equivalent || C
? || Z
? || Description

*: Instructions available in long forms on 16-bit models with extended instruction set.

†: Instruction only available on 16-bit models with extended instruction set.

Padauk microcontrollers (13, 14, 15 or 16 bit)

Padauk Technology make a series of PIC-like microcontrollers notable for their extremely low cost, beginning at {{USD|0.033}} in quantity,{{cite web

|title=What's up with these 3-cent microcontrollers? (A review of the Padauk PMS150C and friends)

|first=Jay |last=Carlson

|url=https://jaycarlson.net/2019/09/06/whats-up-with-these-3-cent-microcontrollers/

|date=6 September 2019 |access-date=2020-05-18

}} with many models costing less than {{USD|0.10}}.{{cite web

|title=The "terrible" 3 cent MCU – a short survey of sub $0.10 microcontrollers.

|website=Tim's blog

|url=https://cpldcpu.word-press.com/2019/08/12/the-terrible-3-cent-mcu/

|date=12 August 2019 |access-date=2020-05-18

}}

{{cite web

|title= Free PDK Documentation

|url=https://free-pdk.github.io/

|quote=Padauk µCs sport an interesting architecture that can be a seen as a ... extension of the Microchip PIC architecture.

}}

{{cite web

|title= Chiptunes on an ATtiny4 and the 3 Cent Micro: Porting to Padauk

|url=https://gir.st/chiptunes.html

|quote=According to some, Padauk's instruction set is heavily inspired by older PICs, with most operations taking place on a single accumulator register.

}}

Although clearly derived from the Microchip PIC12 series,

Jenny List

[https://hackaday.com/2019/08/28/everything-you-want-to-know-about-the-cheapest-processors-available/ "Everything you want to know about the cheapest processors available"].

2019.

there are some significant differences:

  • They do not use the FSR/INDF mechanism for performing indirect memory access, instead having indirect load and store instructions which use an arbitrary RAM location as a pointer;
  • they use a RAM-based call stack, with a stack pointer register;
  • the carry flag uses a "borrow bit" convention for subtracts, rather than the "carry bit" convention used by Microchip;
  • they also include a signed overflow flag, which like the digit carry, is set by add, subtract and compare instructions (every instruction which sets the carry flag except for shift instructions);
  • they have separate RAM and I/O register addresses spaces (64 and 32 bytes, respectively, in the 13-bit instruction set);
  • bit operations are limited to the I/O space and first 16 RAM addresses;
  • the single-operand instructions with a memory source and accumulator destination are omitted;
  • single-operand instructions with accumulator source and destination are provided;
  • subtraction operations compute destination − source, exchanging input operands depending on the destination;
  • they operate faster, requiring 1 cycle for most instructions and 2 cycles for control transfers; and
  • some models support temporal multithreading, having multiple execution contexts whose execution is interleaved.

class="wikitable" style="text-align:center"

|+ 13-bit Padauk instruction set{{cite web |title=Documentation for PADAUK FPPA MCUs |first=Ash "Ninji" |last=Wolf |website=GitHub |date=12 December 2018 |access-date=2020-05-18 |url=https://github.com/free-pdk/fppa-pdk-documentation}}{{cite web |url=http://www.padauk.com.tw/upload/doc/PMC150,%20PMS150%20datasheet%20V108_EN_20181211.pdf#page=38 |title=PMC150/PMS150 8-bit OTP Type IO Controller |type=data sheet |version=Version 1.8 |date=11 December 2018 |pages=38–51 |access-date=2020-06-08 |author=Padauk Technology Co. Ltd. |id=PDK-DS-PMX150-EN-V108}}

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colspan=18|
0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=4| opcode ||colspan=5| Miscellaneous instructions
0000000000000align=left| NOPalign=left| NOPalign=left| No operation
bgcolor=lightgrey

| 0

000000000001colspan=5 align=left| (reserved)
bgcolor=lightgrey

| 0

00000000001xcolspan=5 align=left| (reserved)
bgcolor=lightgrey

| 0

00000000010xcolspan=5 align=left| (reserved)
0000000000110align=left| LDSPTLbgcolor=lightgrey| —align=left rowspan=2| A ← ROM[[SP]], load low/high byte of ROM word using 16-bit pointer on top of stack
0000000000111align=left| LDSPTHbgcolor=lightgrey| —
bgcolor=lightgrey

| 0

000000001colspan=3| —colspan=5 align=left| (reserved)
colspan=18|
0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=4| opcode ||colspan=5| One-operand instructions on accumulator
Same as one-operand instructions on memory (below) except
0000000010111align=left| PCADD Abgcolor=lightgrey align=left| ≈ADDWF PCL,1align=left| PC ← PC + A, add to program counter (not {{s|XCH A}})
0000000011110align=left| SWAP Abgcolor=lightgrey| —align=left| A ← A<<4 | A>>4, swap nibbles (not {{s|CEQSN A}})
colspan=18|
bgcolor=lightgrey

| 0

00000010colspan=4| —colspan=5 align=left| (reserved)
0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 ||colspan=4| opcode ||colspan=5| System control instructions
0000000110000align=left| WDRESETalign=left| CLRWDTalign=left| Restart watchdog timer
bgcolor=lightgrey

| 0

000000110001colspan=5 align=left| (reserved)
0000000110010align=left| PUSHAFbgcolor=lightgrey| —align=left| Push A then flags on top of stack
0000000110011align=left| POPAFbgcolor=lightgrey| —CZalign=left| Pop flags then A from top of stack
bgcolor=lightgrey

| 0

000000110100colspan=5 align=left| (reserved)
0000000110101align=left| RESETalign=left| RESETalign=left| Software reset
0000000110110align=left| STOPSYSalign=left| SLEEPalign=left| Go into standby mode (clock stopped)
0000000110111align=left| STOPEXEbgcolor=lightgrey| —align=left| Go into standby mode (clock running)
0000000111000align=left| ENGINTalign=left| BSF INTCON,GIEalign=left| Enable interrupts
0000000111001align=left| DISGINTalign=left| BCF INTCON,GIEalign=left| Disable interrupts
0000000111010align=left| RETalign=left| RETURNalign=left| Return from subroutine, A unmodified
0000000111011align=left| RETIalign=left| RETFIEalign=left| Return from interrupt
0000000111100align=left| MULbgcolor=lightgrey| —align=left| MULRH:A ← A × MULOP (not all models)
bgcolor=lightgrey

| 0

000000111101colspan=5 align=left| (reserved)
bgcolor=lightgrey

| 0

00000011111xcolspan=5 align=left| (reserved)
colspan=18|
0 || 0 || 0 || 0 || 0 ||colspan=3| opcode ||colspan=5| ioaddr ||colspan=5| Byte-wide I/O operations
00000011colspan=5| ioaddralign=left| XOR ioaddr,Abgcolor=lightgrey| —align=left| IO[ioaddr] ← A ^ IO[address]
00000100colspan=5| ioaddralign=left| MOV ioaddr,Abgcolor=lightgrey| —align=left| IO[ioaddr] ← A
00000101colspan=5| ioaddralign=left| MOV A,ioaddrbgcolor=lightgrey| —Zalign=left| A ← IO[ioaddr]
colspan=18|
0 || 0 || 0 || 0 || 0 || 1 || 1 || c ||colspan=4| address || c ||colspan=5| 16-bit operations (RAM address limited, even)
00000110colspan=4| address0align=left| STT16 addrbgcolor=lightgrey| —align=left| Timer16 ← [address]
00000110colspan=4| address1align=left| LDT16 addrbgcolor=lightgrey| —align=left| [address] ← Timer16
00000111colspan=4| address0align=left| IDXM addr,Abgcolor=lightgrey| —align=left| [[address]] ← A, indirect memory address
00000111colspan=4| address1align=left| IDXM A,addrbgcolor=lightgrey| —align=left| A ← [[address]], indirect memory address
colspan=18|
0 || 0 || 0 || 0 || 1 ||colspan=8| k ||colspan=5| Return literal constant
00001colspan=8| kalign=left| RET kalign=left| RETLW kalign=left| A ← k, then return from subroutine
colspan=18|
0 || 0 || 0 || 1 || c ||colspan=3| bit || c ||colspan=4| address ||colspan=5| Bit operations with RAM (first 16 bytes only)
00010colspan=3| bit0colspan=4| addressalign=left| T0SN addr.balign=left| BTFSC addr,balign=left| Skip if bit b of [addr] is clear
00010colspan=3| bit1colspan=4| addressalign=left| T1SN addr.balign=left| BTFSS addr,balign=left| Skip if bit b of [addr] is set
00011colspan=3| bit0colspan=4| addressalign=left| SET0 addr.balign=left| BCF addr,balign=left| Clear bit b of [addr]
00011colspan=3| bit1colspan=4| addressalign=left| SET1 addr.balign=left| BSF addr,balign=left| Set bit b of [addr]
colspan=18|
0 || 0 || 1 || d ||colspan=3| opcode ||colspan=6| address ||colspan=5| ALU operations between A and memory
0010000colspan=6| addressalign=left| ADD addr,Aalign=left| ADDWF addr,1CZalign=left| [addr] ← [addr] + A
0010001colspan=6| addressalign=left| SUB addr,Aalign=left| SUBWF addr,1CZalign=left| [addr] ← [addr] − A
0010010colspan=6| addressalign=left| ADDC addr,Aaligh=left| ADDWFC addr,1CZalign=left| [addr] ← [addr] + A + C
0010011colspan=6| addressalign=left| SUBC addr,Abgcolor=lightgrey align=left| ≈SUBWFB addr,1CZalign=left| [addr] ← [addr] − A − C
0010100colspan=6| addressalign=left| AND addr,Aalign=left| ANDWF addr,1Zalign=left| [addr] ← [addr] & A, logical and
0010101colspan=6| addressalign=left| OR addr,Aalign=left| IORWF addr,1Zalign=left| [addr] ← [addr] {{!}} A, logical inclusive or
0010110colspan=6| addressalign=left| XOR addr,Aalign=left| XORWF addr,1Zalign=left| [addr] ← [addr] ^ A, logical exclusive or
0010111colspan=6| addressalign=left| MOV addr,Aalign=left| MOVWF addralign=left| [addr] ← A
0011000colspan=6| addressalign=left| ADD A,addralign=left| ADDWF addr,0CZalign=left| A ← A + [addr]
0011001colspan=6| addressalign=left| SUB A,addrbgcolor=lightgrey align=left| ≠SUBWF addr,0CZalign=left| A ← A − [addr]
0011010colspan=6| addressalign=left| ADDC A,addraligh=left| ADDWFC addr,0CZalign=left| A ← A + [addr] + C
0011011colspan=6| addressalign=left| SUBC A,addrbgcolor=lightgrey align=left| ≠SUBWFB addr,0CZalign=left| A ← A − [addr] − C
0011100colspan=6| addressalign=left| AND A,addralign=left| ANDWF addr,0Zalign=left| A ← [A] & [addr], logical and
0011101colspan=6| addressalign=left| OR A,addralign=left| IORWF addr,0Zalign=left| A ← A {{!}} [addr], logical inclusive or
0011110colspan=6| addressalign=left| XOR A,addralign=left| XORWF addr,0Zalign=left| A ← A ^ [addr], logical exclusive or
0011111colspan=6| addressalign=left| MOV A,addralign=left| MOVF addr,0Zalign=left| A ← [addr]
colspan=18|
0 || 1 || 0 ||colspan=4| opcode ||colspan=6| address ||colspan=5| One-operand operations on memory
0100000colspan=6| addressalign=left| ADDC addrbgcolor=lightgrey| —CZalign=left| [addr] ← [addr] + C
0100001colspan=6| addressalign=left| SUBC addrbgcolor=lightgrey| —CZalign=left| [addr] ← [addr] − C
0100010colspan=6| addressalign=left| IZSN addralign=left| INCFSZ addr,1CZalign=left| [addr] ← [addr] + 1, then skip if zero
0100011colspan=6| addressalign=left| DZSN addralign=left| DECFSZ addr,1CZalign=left| [addr] ← [addr] − 1, then skip if zero
0100100colspan=6| addressalign=left| INC addralign=left| INCF addr,1CZalign=left| [addr] ← [addr] + 1
0100101colspan=6| addressalign=left| DEC addralign=left| DECF addr,1CZalign=left| [addr] ← [addr] − 1
0100110colspan=6| addressalign=left| CLEAR addrbgcolor=lightgrey align=left| ≈CLRF addralign=left| [addr] ← 0
0100111colspan=6| addressalign=left| XCH addrbgcolor=lightgrey| —align=left| A ← [addr], [addr] ← A
0101000colspan=6| addressalign=left| NOT addralign=left| COMF addr,1Zalign=left| [addr] ← ~[addr], bitwise complement
0101001colspan=6| addressalign=left| NEG addrbgcolor=lightgrey| —Zalign=left| [addr] ← −[addr], negate
0101010colspan=6| addressalign=left| SR addrbgcolor=lightgrey align=left| ≈LSRF addr,1Calign=left| [addr] ← [addr] >> 1, logical shift right
0101011colspan=6| addressalign=left| SL addrbgcolor=lightgrey align=left| ≈LSLF addr,1Calign=left| [addr] ← [addr] << 1, shift left
0101100colspan=6| addressalign=left| SRC addralign=left| RRF addr,1Calign=left| [addr] ← C << 7 {{!}} [addr] >> 1, rotate right through carry
0101101colspan=6| addressalign=left| SLC addralign=left| RLF addr,1Calign=left| [addr] ← [addr] << 1 {{!}} C, rotate left through carry
0101110colspan=6| addressalign=left| CEQSN addrbgcolor=lightgrey| —CZalign=left| Compute A − [addr], then skip if zero
bgcolor=lightgrey

| 0

101111colspan=6| addressalign=left colspan=5| (reserved for CNEQSN)
colspan=18|
0 || 1 || 1 ||colspan=2| opc ||colspan=3| bit ||colspan=5| address ||colspan=5| Bit operations with I/O
01100colspan=3| bitcolspan=5| addressalign=left| T0SN ioaddr.balign=left| BTFSC ioaddr,balign=left| Skip if bit b of [ioaddr] is clear
01101colspan=3| bitcolspan=5| addressalign=left| T1SN ioaddr.balign=left| BTFSS ioaddr,balign=left| Skip if bit b of [ioaddr] is set
01110colspan=3| bitcolspan=5| addressalign=left| SET0 ioaddr.balign=left| BCF ioaddr,balign=left| Clear bit b of [ioaddr]
01111colspan=3| bitcolspan=5| addressalign=left| SET1 ioaddr.balign=left| BSF ioaddr,balign=left| Set bit b of [ioaddr]
colspan=18|
1 || 0 ||colspan=3| opcode ||colspan=8| literal ||colspan=5| Literal operations: A ← OP(A,k)
10000colspan=8| kalign=left| ADD A,kalign=left| ADDLW kCZalign=left| A ← A + k
10001colspan=8| kalign=left| SUB A,kbgcolor=lightgrey align=left| ≠SUBLW kCZalign=left| A ← A − k
10010colspan=8| kalign=left| CEQSN A,kbgcolor=lightgrey| —CZalign=left| Compute A − k, then skip if zero
bgcolor=lightgrey

| 1

0011colspan=8| kalign=left colspan=5| (reserved for CNEQSN)
10100colspan=8| kalign=left| AND A,kbgcolor=lightgrey align=left| ≈ANDLW kZalign=left| A ← A & k
10101colspan=8| kalign=left| OR A,kbgcolor=lightgrey align=left| ≈IORLW kZalign=left| A ← A {{!}} k
10110colspan=8| kalign=left| XOR A,kbgcolor=lightgrey align=left| ≈XORLW kZalign=left| A ← A ^ k
10111colspan=8| kalign=left| MOV A,kalign=left| MOVLW kalign=left| A ← k
colspan=18|
1 || 1 || c ||colspan=10| k ||colspan=5| Control transfers: PC ← k
110colspan=10| kalign=left| GOTO kalign=left| GOTO kalign=left| PC ← k
111colspan=10| kalign=left| CALL kalign=left| CALL kalign=left| Push PC, then PC ← k
colspan=18|
1
2 || 1
1 || 1
0 ||
9 ||
8 ||
7 ||
6 ||
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4 ||
3 ||
2 ||
1 ||
0 || Mnemonic || PIC
equivalent || C
? || Z
? || Description

The 14-, 15- and 16-bit instruction sets primarily differ in having wider address fields, although some encoding changes are made to allow a few additional instructions (such as {{code|CNEQSN}}, which performs a compare and skip if not equal.)

class="wikitable" style="text-align:center"

|+ 14-bit Padauk instruction set{{cite web |title=PADAUK FPPA core devices (14 bit) instruction set |first=Ash "Ninji" |last=Wolf |date=23 May 2020 |access-date=2020-06-08 |url=https://free-pdk.github.io/PADAUK_FPPA_14_bit_instruction_set.html}}{{cite web |url=http://www.padauk.com.tw/upload/doc/PFS154%20datasheet_v104_EN_20190618.pdf#page=71 |title=PFS154 8bit MTP Type IO controller Data Sheet |version=Version 1.04 |date=18 June 2019 |pages=71–84 |access-date=2020-06-09 |author=Padauk Technology Co. Ltd. |id=PDK-DS-PFS154_RN_V104}}

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colspan=19|
0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=4| opcode ||colspan=5| Miscellaneous instructions same as 13-bit
bgcolor=lightgrey

| 0

000000001colspan=4| —colspan=5 align=left| (reserved)
bgcolor=lightgrey

| 0

00000001colspan=5| —colspan=5 align=left| (reserved)
bgcolor=lightgrey

| 0

00000010colspan=5| —colspan=5 align=left| (reserved)
0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 ||colspan=4| opcode ||colspan=5| One-operand instructions on A same as 13-bit
0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 ||colspan=4| opcode ||colspan=5| System control instructions same as 13-bit
bgcolor=lightgrey

| 0

0000010colspan=6| —colspan=5 align=left| (reserved)
colspan=18|
0 || 0 || 0 || 0 || 0 ||colspan=3| opcode ||colspan=6| address ||colspan=5| Byte-wide I/O operations same as 13-bit, but opcodes changed
00000011colspan=6| ioaddralign=left| XOR ioaddr,Abgcolor=lightgrey| —align=left| IO[ioaddr] ← A ^ IO[address]
bgcolor=lightgrey

| 0

000010colspan=7| —colspan=5 align=left| (reserved)
00000110colspan=6| ioaddralign=left| MOV ioaddr,Abgcolor=lightgrey| —align=left| IO[ioaddr] ← A
00000111colspan=6| ioaddralign=left| MOV A,ioaddrbgcolor=lightgrey| —Zalign=left| A ← IO[ioaddr]
colspan=19|
0 || 0 || 0 || 0 || 1 || 0 ||colspan=8| k ||colspan=5| Return literal constant same as 13-bit
0 || 0 || 0 || 0 || 1 || 1 || c ||colspan=6| address || c ||colspan=5| 16-bit operations same as 13-bit, but 128-byte range
colspan=19|
0 || 0 || 0 || 1 || 0 ||colspan=3| bit ||colspan=6| address ||colspan=5| Copy bit to I/O
00010colspan=3| bitcolspan=6| addressalign=left| SWAPC ioaddr.bbgcolor=lightgrey| —Calign=left| Swap carry with [ioaddr] bit b
colspan=19|
0 || 0 || 0 || 1 || 1 || c || d ||colspan=7| address ||colspan=5| Additional 2-operand operations
0001100colspan=7| addressalign=left| COMP A,addrbgcolor=lightgrey| —CZalign=left| A − [addr], flags set, result discarded
0001101colspan=7| addressalign=left| COMP addr,Abgcolor=lightgrey| —CZalign=left| [addr] − A, flags set, result discarded
0001110colspan=7| addressalign=left| NADD A,addralign=left| SUBWF addr,0CZalign=left| A ← [addr] + −A (A ← [addr] + ~A + 1)
0001111colspan=7| addressalign=left| NADD addr,Abgcolor=lightgrey| —CZalign=left| [addr] ← A + −[addr] ([addr] ← A + ~[addr] + 1)
colspan=19|
0 || 0 || 1 || d ||colspan=3| opcode ||colspan=7| address ||colspan=5| 2-operand instructions same as 13-bit
colspan=19|
0 || 1 || 0 ||colspan=4| opcode ||colspan=7| address ||colspan=5| One-operand operations on memory same as 13-bit, plus CNEQSN
0101111colspan=7| addressalign=left| CNEQSN addrbgcolor=lightgrey| —CZalign=left| Compute A − [addr], then skip if non-zero
colspan=19|
0 || 1 || 1 ||colspan=2| opc ||colspan=3| bit ||colspan=6| ioaddr ||colspan=5| Bit operations with I/O same as 13-bit, but 64-byte range
1 || 0 || 0 ||colspan=2| opc ||colspan=3| bit ||colspan=6| address ||colspan=5| Bit operations with memory same as 13-bit, but 64-byte range
colspan=19|
1 || 0 || 1 ||colspan=3| opcode ||colspan=8| literal ||colspan=5| Literal operations same as 13-bit, plus CNEQSN
101011colspan=8| kalign=left| CNEQSN A,kbgcolor=lightgrey| —CZalign=left| Compute A − k, then skip if non-zero
colspan=19|
1 || 1 || c ||colspan=11| k ||colspan=5| Control transfers same as 13-bit
colspan=19|
1
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2 || 1
1 || 1
0 ||
9 ||
8 ||
7 ||
6 ||
5 ||
4 ||
3 ||
2 ||
1 ||
0 || Mnemonic || PIC
equivalent || C
? || Z
? || Description

PIC18 high end core devices (16 bit)

In 2000, Microchip introduced the PIC18 architecture.{{Cite web |title=Martin Dubuc's SDCC PIC18F Project Page |url=http://mdubuc.freeshell.org/Sdcc/ |access-date=2025-02-24 |website=mdubuc.freeshell.org}} Unlike the 17 series, it has proven to be very popular, with a large number of device variants presently in manufacture. In contrast to earlier devices, which were more often than not programmed in assembly, C has become the predominant development language.{{Cite web|url=http://www.microchipc.com/sourcecode/|title = Microchip PIC micros and C - source and sample code}}

The PIC18 has a 12-bit RAM address space, divided into 16 pages of 256 bytes. The 8-bit f field determines the address in combination with the a bit and the 4-bit bank select register (BSR). If a=0, the BSR is ignored and the f field is sign-extended to the range 0x000–0x07F (global RAM) or 0xF80–0xFFF (special function registers). If a=1, the f field is extended with the BSR to generate the 12-bit address.

The PIC18 extends the FSR/INDF mechanism used in previous PICmicro processors for indirect addressing in two ways:

First, it provides three file select registers. The FSRn registers are 12 bits long (each split into two 8-bit portions FSR0L through FSR2H), and access to the corresponding INDFn register (INDF0 through INDF2) acts as an alias for the addressed byte.

Second, there are addressing modes. For each of the three, there is not just one INDFn register, but five, and the one used determines the addressing mode:

  • INDFn: Access the byte at location FSRn
  • POSTDECn: Access the byte at FSRn, then decrement FSRn
  • POSTINCn: Access the byte at FSRn, then increment FSRn
  • PREINCn: Increment FSRn, then access the byte at the incremented FSRn
  • PLUSWn: Access the byte at FSRn + W (indexed addressing).

There are also instructions to directly load an FSR pair with a 12-bit address, and a MOVFF instruction that moves a byte between two 12-bit addresses.

class="wikitable" style="text-align:center"

|+ PIC18 16-bit instruction set{{Citation |url=http://ww1.microchip.com/downloads/en/DeviceDoc/39605F.pdf |title=PIC18F1220/1320 Data Sheet |year=2007 |author=Microchip Technology, Inc. |access-date=2012-04-02}}

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2 ||
1 ||
0 || Mnemonic || C
? || Z
? || N
? || Description
colspan=21|
0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=8| opcode ||colspan=5| Miscellaneous instructions
0000000000000000align=left| NOPalign=left| No operation
0000000000000011align=left| SLEEPalign=left| Go into standby mode
0000000000000100align=left| CLRWDTalign=left| Restart watchdog timer
0000000000000101align=left| PUSHalign=left| Push PC on top of stack
0000000000000110align=left| POPalign=left| Pop (and discard) top of stack
0000000000000111align=left| DAWCalign=left| Decimal adjust W
0000000000001000align=left| TBLRD∗align=left| Table read: TABLAT ← mem[TBLPTR]
0000000000001001align=left| TBLRD∗+align=left| Table read with postincrement
0000000000001010align=left| TBLRD∗−align=left| Table read with postdecrement
0000000000001011align=left| TBLRD+∗align=left| Table read with pre-increment
00000000000011colspan=2| modalign=left| TBLWRalign=left| Table write, same modes as TBLRD
000000000001000salign=left| RETFIE [, FAST]align=left| Return from interrupt
000000000001001salign=left| RETURN [, FAST]align=left| Return from subroutine
0000000000010100align=left| CALLW*align=left| Push PC, jump to PCLATU:PCLATH:W
0000000011111111align=left| RESET000align=left| Software reset
colspan=21|
00000001style="background:lightgrey;" colspan=4| —0—colspan=4| kalign=left| MOVLBalign=left| Move literal k to bank select register
0 || 0 || 0 || 0 || 1 ||colspan=3| opcode ||colspan=8| literal ||colspan=5| Literal operations: W ← OP(k,W)
00001000colspan=8| kalign=left| SUBLW kalign=left| W ← k − W
00001001colspan=8| kalign=left| IORLW kalign=left| W ← k {{pipe}} W, logical inclusive or
00001010colspan=8| kalign=left| XORLW kalign=left| W ← k ^ W, exclusive or
00001011colspan=8| kalign=left| ANDLW kalign=left| W ← k & W, logical and
00001100colspan=8| kalign=left| RETLW kalign=left| RETURN W ← k
00001101colspan=8| kalign=left| MULLW kalign=left| W ← k × W
00001110colspan=8| kalign=left| MOVLW kalign=left| W ← k
00001111colspan=8| kalign=left| ADDLW kalign=left| W ← k + W
colspan=21|
0 ||colspan=5| opcode || d || a ||colspan=8| register ||colspan=5| ALU operations: dest ← OP(f,W)
0000001acolspan=8| falign=left| MULWF f,aalign=left| PRODH:PRODL ← W × f (unsigned)
000001dacolspan=8| falign=left| DECF f,d,aCZNalign=left| dest ← f − 1
000100dacolspan=8| falign=left| IORWF f,d,aZNalign=left| dest ← f {{pipe}} W, logical inclusive or
000101dacolspan=8| falign=left| ANDWF f,d,aZNalign=left| dest ← f & W, logical and
000110dacolspan=8| falign=left| XORWF f,d,aZNalign=left| dest ← f ^ W, exclusive or
000111dacolspan=8| falign=left| COMF f,d,aZNalign=left| dest ← ~f, bitwise complement
001000dacolspan=8| falign=left| ADDWFC f,d,aCZNalign=left| dest ← f + W + C
001001dacolspan=8| falign=left| ADDWF f,d,aCZNalign=left| dest ← f + W
001010dacolspan=8| falign=left| INCF f,d,aCZNalign=left| dest ← f + 1
001011dacolspan=8| falign=left| DECFSZ f,d,aalign=left| dest ← f − 1, skip if 0
001100dacolspan=8| falign=left| RRCF f,d,aCZNalign=left| dest ← f>>1 {{pipe}} C<<7, rotate right through carry
001101dacolspan=8| falign=left| RLCF f,d,aCZNalign=left| dest ← f<<1 {{pipe}} C, rotate left through carry
001110dacolspan=8| falign=left| SWAPF f,d,aalign=left| dest ← f<<4 {{pipe}} f>>4, swap nibbles
001111dacolspan=8| falign=left| INCFSZ f,d,aalign=left| dest ← f + 1, skip if 0
010000dacolspan=8| falign=left| RRNCF f,d,aZNalign=left| dest ← f>>1 {{pipe}} f<<7, rotate right (no carry)
010001dacolspan=8| falign=left| RLNCF f,d,aZNalign=left| dest ← f<<1 {{pipe}} f>>7, rotate left (no carry)
010010dacolspan=8| falign=left| INFSNZ f,d,aalign=left| dest ← f + 1, skip if not 0
010011dacolspan=8| falign=left| DCFSNZ f,d,aalign=left| dest ← f − 1, skip if not 0
010100dacolspan=8| falign=left| MOVF f,d,aZNalign=left| dest ← f
010101dacolspan=8| falign=left| SUBFWB f,d,aCZNalign=left| dest ← W + ~f + C (dest ← W − f − C̅)
010110dacolspan=8| falign=left| SUBWFB f,d,aCZNalign=left| dest ← f + ~W + C (dest ← f − W − C̅)
010111dacolspan=8| falign=left| SUBWF f,d,aCZNalign=left| dest ← f − W (dest ← f + ~W + 1)
colspan=21|
0 || 1 || 1 || 0 ||colspan=3| opcode || a ||colspan=8| register ||colspan=5| ALU operations, do not write to W
0110000acolspan=8| falign=left| CPFSLT f,aalign=left| skip if f < W (unsigned)
0110001acolspan=8| falign=left| CPFSEQ f,aalign=left| skip if f == W
0110010acolspan=8| falign=left| CPFSGT f,aalign=left| skip if f > W (unsigned)
0110011acolspan=8| falign=left| TSTFSZ f,aalign=left| skip if f == 0
0110100acolspan=8| falign=left| SETF f,aalign=left| f ← 0xFF
0110101acolspan=8| falign=left| CLRF f,a1align=left| f ← 0, PSR.Z ← 1
0110110acolspan=8| falign=left| NEGF f,aCZNalign=left| f ← −f
0110111acolspan=8| falign=left| MOVWF f,aalign=left| f ← W
colspan=21|
0111colspan=3| bitacolspan=8| falign=left| BTG f,b,aalign=left| Toggle bit b of f
1 || 0 ||colspan=2| opc ||colspan=3| bit || a ||colspan=8| register ||colspan=5| Bit operations
1000colspan=3| bitacolspan=8| falign=left| BSF f,b,aalign=left| Set bit b of f
1001colspan=3| bitacolspan=8| falign=left| BCF f,b,aalign=left| Clear bit b of f
1010colspan=3| bitacolspan=8| falign=left| BTFSS f,b,aalign=left| Skip if bit b of f is set
1011colspan=3| bitacolspan=8| falign=left| BTFSC f,b,aalign=left| Skip if bit b of f is clear
colspan=21|
1 || 1 || 0 ||colspan=2| opc ||colspan=12| address ||colspan=5| Large-address operations
1100colspan=12| sourcestyle="text-align:left;" rowspan="2"| MOVFF s,drowspan=2|rowspan=2|rowspan=2|style="text-align:left;" rowspan="2"| Move absolute
1111colspan=12| destination
11010colspan=11| nalign=left| BRA nalign=left| Branch to PC + 2n
11011colspan=11| nalign=left| RCALL nalign=left| Subroutine call to PC + 2n
colspan=21|
1 || 1 || 1 || 0 || 0 ||colspan=3| cond ||colspan=8| n ||colspan=5| Conditional branch (to PC+2n)
11100000colspan=8| nalign=left| BZ nalign=left| Branch if PSR.Z is set
11100001colspan=8| nalign=left| BNZ nalign=left| Branch if PSR.Z is clear
11100010colspan=8| nalign=left| BC nalign=left| Branch if PSR.C is set
11100011colspan=8| nalign=left| BNC nalign=left| Branch if PSR.C is clear
11100100colspan=8| nalign=left| BOV nalign=left| Branch if PSR.V is set
11100101colspan=8| nalign=left| BNOV nalign=left| Branch if PSR.V is clear
11100110colspan=8| nalign=left| BN nalign=left| Branch if PSR.N is set
11100111colspan=8| nalign=left| BNN nalign=left| Branch if PSR.N is clear
colspan=21|
1 || 1 || 1 || 0 || 1 || 0 ||colspan=2| opc ||colspan=8| k ||colspan=5| Extensions for using FSR2 as software stack pointer*
11101000colspan=2| ncolspan=6| kalign=left| ADDFSR n,k*align=left| FSRn += k
1110100011colspan=6| kalign=left| ADDULNK k*align=left| FSR2 += k, pop PC
11101001colspan=2| ncolspan=6| kalign=left| SUBFSR n,k*align=left| FSRn −= k
1110100111colspan=6| kalign=left| SUBULNK k*align=left| FSR2 −= k, pop PC
11101010colspan=8| kalign=left| PUSHL k*align=left| [FSR2] ← k, decrement FSR2
111010110colspan=7| srowspan=2 align=left| MOVSF src,f{{hair space}}*rowspan=2|rowspan=2|rowspan=2|rowspan=2 align=left| f ← FSR2[s]
1111colspan=12| f
111010111colspan="7" |srowspan=2 align=left| MOVSS src,dst*rowspan="2" |rowspan=2|rowspan=2|rowspan=2 align=left| FSR2[d] ← FSR2[s]
1111colspan=5 style="background:lightgrey;| —0—colspan=7| d
colspan=21|
1 || 1 || 1 || 0 || 1 || 1 ||colspan=2| opc ||colspan=8| k ||colspan=5| 2-word instructions
1110110scolspan=8| k (lsbits)style="text-align:left;" rowspan="2"| CALL k[, FAST]rowspan=2|rowspan=2|rowspan=2|style="text-align:left;" rowspan="2"| Call subroutine (20-bit address)
1111colspan=12| k (msbits)
11101110style="background:lightgrey;"| 0style="background:lightgrey;"| 0colspan=2| fcolspan=4| k (msb)style="text-align:left;" rowspan="2"| LFSR f,krowspan=2|rowspan=2|rowspan=2|style="text-align:left;" rowspan="2"| Move 12-bit literal to FSRf
11110000colspan=8| k (lsbits)
11101111colspan=8| k (lsbits)style="text-align:left;" rowspan="2"| GOTO krowspan=2|rowspan=2|rowspan=2|style="text-align:left;" rowspan="2"| Absolute jump, PC ← k (20-bit address)
1111colspan=12| k (msbits)
colspan=21|
1 || 1 || 1 || 1 ||colspan=12| k ||colspan=5| No operation, second word of 2-word instructions
colspan=21|
1
5 || 1
4 || 1
3 || 1
2 || 1
1 || 1
0 ||
9 ||
8 ||
7 ||
6 ||
5 ||
4 ||
3 ||
2 ||
1 ||
0 || Mnemonic || C
? || Z
? || N
? || Description

*: These extended instructions are only available on some models, and then only if the XINST configuration bit is set.

Hycon clones (16 bit)

Hycon Technology make a series of microcontrollers (part number prefixes HY10 through HY17) with an "H08" CPU core which is very similar to the PIC18. Although the opcode assignments do not appear to be publicly documented,The [https://www.hycontek.com/hy_mcu/APD-HYIDE006_EN.pdf#page=23 HYCON-IDE Software User's Manual] shows a few opcodes on pp. 23–26, which do not match the PIC18. the H08A instruction set is very similar to the PIC18 one. There are numerous mnemonic changes (for example, an unconditional relative branch is called BRA by Microchip but JR by Hycon), and a small number of functional changes:{{cite web

|title=Instruction Set H08A User’s Manual

|url=https://www.hycontek.com/wp-content/uploads/APD-CORE002_EN.pdf

|publisher=Hycon Technology

|date=1 August 2010

|id=APD-CORE002-V03_EN

|access-date=2025-01-04

}}

  • The H08A only has two FSR/IND registers, not three.
  • The H08A has a smaller 14-bit ROM space and 11-bit RAM space (vs. up to 20 and 12 bits on the PIC18), but it is not clear if this is an architectural limit or just that of current products.
  • The H08A is missing the PIC18 PUSH, DAW, TBLWR, CALLW, RESET, MOVF, SUBFWB, and NEGF instructions.
  • In lieu of the PIC18's MOVF instruction, the H08 has MVF, which moves W to a memory location f, but does not set the flags.
  • The H08A only supports TBLR * and TBLR *+; it has no equivalent to the PIC18's TBLRD *- or TBLRD +*.
  • The H08 CLRF instruction does not alter the Z flag (the PIC18's sets it).
  • In addition to the PIC18's four rotate instructions, the H08A has ARLC (identical to RLCF, but also sets the overflow flag if the sign bit changes) and ARRC, which is an arithmetic right shift, preserving the msbit of the source.
  • The H08A has a MVLP instruction which copies a 14-bit immediate value to the ROM table pointer registers.
  • In addition to SLP, the H08A has an IDLE instruction.

There is also a reduced H08B variant. This differs from the H08A in that:{{cite web

|title=Instruction Set H08B User’s Manual

|url=https://www.hycontek.com/hy_mcu/APD-CORE003_EN.pdf

|publisher=Hycon Technology

|date=1 August 2010

|id=APD-CORE003-V02_EN

|access-date=2025-01-04

}}{{cite web

|title=CPU Core Application Description: Comparisons and Supplements of Instruction Set H08A and H08B

|publisher=Hycon Technology

|date=24 March 2011

|id=PD-CORE001_EN-V06

|url=https://www.hycontek.com/hy_mcu/APD-CORE001_EN.pdf#page=3

|access-date=2025-01-04

}} This documents a PIC18-like PUSH instruction on the H08A, although other Hycon manuals do not.

  • The H08B has only a single FSR/INDF register pair.
  • Some,{{cite web

|title=HY14E10/HY14E10M User’s Guide Digital Pressure Sensor Platform

|publisher=Hycon Technology

|date=25 December 2016

|id=UG-HY14E10-V06_EN

|page=14

|url=https://www.hycontek.com/hy_mcu/UG-HY14E10_EN.pdf#page=14

|access-date=2025-01-04

}} but not all{{cite web

|title=HY10P Family User’s Guide Mixed Signal Microcontroller

|publisher=Hycon Technology

|date=17 November 2017

|id=UG-HY10S40-V07_EN

|page=18

|url=https://www.hycontek.com/hy_mcu/UG-HY10S40_TC.pdf#page=18

|access-date=2025-01-04

}} also lack the PIC18's additional addressing mode registers and have only the basic FSR0/INDF0 pair.

  • It lacks the H08A's ARLC, ARRC and MVLP instructions.
  • It lacks the shadow registers used for the PIC18 and H08A's "fast" call/return option.
  • It lacks equivalents to the PIC18's multiply (MULLW and MULWF), relative branch (BRA, RCALL and conditional branch BZ through BNN), MOVLB, LFSR, MOVFF, POP, and TBLRD instructions.

There are also H08C and H08D variants, which are slightly expanded versions of the H08A, but the additions are not clear.{{cite web

|title=Instruction Set H08A、H08C、H08D User’s Manual

|url=https://www.hycontek.com/hy_mcu/APD-CORE002_EN.pdf#page=4

|publisher=Hycon Technology

|date=1 June 2020

|id=APD-CORE002-V04_EN

|access-date=2025-01-04

}} The H08C{{cite web

|title=HY15S41 User’s Guide Mixed Signal Microcontroller

|publisher=Hycon Technology

|date=16 November 2017

|id=UG-HY15S41-V04_EN

|page=15,17

|url=https://www.hycontek.com/hy_mcu/UG-HY15S41_EN.pdf#page=17

|access-date=2025-01-04

}} and H08D{{cite web

|title=HY17M28 Datasheet 8-Bit RISC-like Mixed Signal Microcontroller, Embedded 24-Bit ΣΔADC, Low Noise Amplifier, LED Driver

|publisher=Hycon Technology

|date=24 July 2023

|id=DS-HY17M28-V01_TC

|page=27

|url=https://www.hycontek.com/hy_mcu/DS-HY17M28_TC.pdf#page=27

|language=zh-Hant

|access-date=2025-01-04

}} (The [https://www.hycontek.com/hy_mcu/DS-HY17M28_EN.pdf#page=27 English datasheet] is currently "under construction".) do include a third FSR2/INDF2 register pair.

PIC24 and dsPIC 16-bit microcontrollers

In 2001, Microchip introduced the dsPIC series of chips,

{{Cite web

|url=http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2018&mcparam=en013529

|title = Microchip Technology debuts world's highest performing 16-bit microcontrollers: dsPIC

|archive-url=https://web.archive.org/web/20041213035811/http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2018&mcparam=en013529

|archive-date=2004-12-13

}}

which entered mass production in late 2004. They are Microchip's first inherently 16-bit microcontrollers. PIC24 devices are designed as general purpose microcontrollers. dsPIC devices include digital signal processing capabilities in addition.

Instructions come in two main varieties. One is like the classic one-operand PIC instructions, with an operation between W0 and a value in a specified f register (i.e. the first 8K of RAM), and a destination select bit selecting which is updated with the result. The W registers are memory-mapped, so the f operand may specify a W register.

The other form, new to the PIC24, specifies three W register operands, two of which allow a 3-bit addressing mode specification:

class="wikitable" style="text-align:center"

|+ PIC24 addressing modes

colspan=3| source operand ||colspan=3| destination operand ||rowspan=2| Description
ppp || Reg || Syntax || qqq || Reg || Syntax
000ssssWs000ddddWdalign=left| Register direct
001ssss[Ws]001dddd[Wd]align=left| Indirect
010ssss[Ws−−]010dddd[Wd−−]align=left| Indirect with postdecrement
011ssss[Ws++]011dddd[Wd++]align=left| Indirect with postincrement
100ssss[−−Ws]100dddd[−−Wd]align=left| Indirect with predecrement
101ssss[++Ws]101dddd[++Wd]align=left| Indirect with preincrement
11kkkkk#u5colspan=3 style="background:lightgrey;"| (Unused, illegal)align=left| 5-bit unsigned immediate
11xssss[Ws+Ww]11xdddd[Wd+Ww]align=left| Indirect with register offset

The register offset addressing mode is only available for the MOV src,dst instruction, where the Ww register may be used as a register offset for the source, destination, or both. All other instructions use this encoding for an unsigned 5-bit immediate source instead.

For the operands to TBLRD and TBLWT which access program memory, only the indirect modes are allowed, and refer to addresses in code memory.

A few instructions are 2 words long. The second word is a NOP, which includes up to 16 bits of additional immediate operand.

class="wikitable" style="text-align:center"

|+ PIC24 24-bit instruction set{{Citation |url=http://ww1.microchip.com/downloads/en/DeviceDoc/70157C.pdf |title=dsPIC30F Programmer's Reference Manual |year=2008 |publisher=Microchip Technology |id=DS70157C |access-date=2012-07-02}}

2
3 || 2
2 || 2
1 || 2
0 || 1
9 || 1
8 || 1
7 || 1
6 || 1
5 || 1
4 || 1
3 || 1
2 || 1
1 || 1
0 ||
9 ||
8 ||
7 ||
6 ||
5 ||
4 ||
3 ||
2 ||
1 ||
0 || Mnemonic || C
? || Z
? || N
? || Description

colspan=29|
0 || 0 || 0 || 0 ||colspan=4| opcode ||colspan=16| offset ||colspan=5| Control transfers
00000000colspan=16| —align=left| NOPalign=left| No operation
00000000style="background:lightgrey;" colspan=9| —0—colspan=7| n<22:16>align=left| CALL/GOTO addr23align=left| (second word)
00000000colspan=16| nalign=left| DO #k,addralign=left| (second word)
colspan=29|
0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 ||colspan=2| opc ||colspan=9| —0— ||colspan=4| a ||colspan=5| Computed control transfer (to 16-bit Wa)
00000001000colspan=9 style="background:lightgrey;"| —0—colspan=4| aalign=left| CALL Raalign=left| Push PC, jump to Wa
00000001001colspan=9 style="background:lightgrey;"| —0—colspan=4| aalign=left| RCALL Raalign=left| Push PC, jump to PC+2×Wa
00000001010colspan=9 style="background:lightgrey;"| —0—colspan=4| aalign=left| GOTO Raalign=left| Jump to Wa
00000001011colspan=9 style="background:lightgrey;"| —0—colspan=4| aalign=left| BRA Raalign=left| Jump to PC+2×Wa
colspan=29|
00000010colspan=15| n<15:1>0style="text-align:left;" rowspan="2"| CALL addr23rowspan=2|rowspan=2|rowspan=2|style="text-align:left;" rowspan="2"| Push PC, jump to absolute address
colspan=8| —0—colspan=9 style="background:lightgrey;"| —0—colspan=7| n<22:16>
style="background:lightgrey;"

| 0

0000011colspan=16| —colspan="5" style="text-align:left;"| (Reserved)
00000100colspan=15| n0style="text-align:left;" rowspan="2"| GOTO addr23rowspan=2|rowspan=2|rowspan=2|style="text-align:left;" rowspan="2"| Jump to absolute address
colspan=8| —0—colspan=9 style="background:lightgrey;"| —0—colspan=7| n<22:16>
style="background:lightgrey;"
000001010Bcolspan=10| kcolspan=4| dalign=left| RETLW[.B] #k,Wdalign=left| Wd = k, pop PC
0000011000colspan=14 style="background:lightgrey;"| —0—align=left| RETURNalign=left| pop PC
0000011001colspan=14 style="background:lightgrey;"| —0—align=left| RETFIECZNalign=left| pop SR, PC
00000111colspan=16| nalign=left| RCALL addressalign=left| Push PC, PC += 2×s16
0000100000colspan=14| kstyle="text-align:left;" rowspan="2"| DO #k,addrrowspan=2|rowspan=2|rowspan=2|style="text-align:left;" rowspan="2"| Zero-overhead loop: k+1 is repeat count, PC+2×n last instruction
colspan=8| —0—colspan=16| n
0000100000colspan=14| kalign=left| REPEAT #kalign=left| Repeat next instruction k+1 times
00001000colspan=16| nalign=left| RCALL addressalign=left| Push PC, PC += 2×s16
style="background:lightgrey;"

| 0

000101colspan=17| —colspan="5" style="text-align:left;"| (Reserved)
0000110acolspan=16| nalign=left| BRA Oa, addrrowspan=2 align=left| If accumulator an overflowed/saturated, PC += 2×simm16
0000111acolspan=16| nalign=left| BRA Sa, addr
colspan=29|
0 ||colspan=4| opcode ||colspan=4| w || B ||colspan=3| q ||colspan=4| d ||colspan=3| p ||colspan=4| s ||colspan=5| Reverse subtract: dest ← source − Ww
00010colspan=4| wBcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| SUBR[.B] Ww,src,dstCZNalign=left| dst ← src − Ww = src + ~Ww + 1)
00011colspan=4| wBcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| SUBBR[.B] Ww,src,dstCZNalign=left| dst ← src − Ww − C̅ = src + ~Ww + C
0010colspan=16| kcolspan=4| dalign=left| MOV #k,Wdalign=left| Wd ← #imm16
colspan=29|
0 || 0 || 1 || 1 ||colspan=4| cond ||colspan=16| n ||colspan=5| Conditional branch to PC+2×n
00110000colspan=16| nalign=left| BRA OV,addralign=left| ...if PSR.V is set
00110001colspan=16| nalign=left| BRA C,addralign=left| ...if PSR.C is set
00110010colspan=16| nalign=left| BRA Z,addralign=left| ...if PSR.Z is set
00110011colspan=16| nalign=left| BRA N,addralign=left| ...if PSR.N is set
00110100colspan=16| nalign=left| BRA LE,addralign=left| ...if PSR.Z, or PSR.N ≠ PSR.V
00110101colspan=16| nalign=left| BRA LT,addralign=left| ...if PSR.N ≠ PSR.V
00110110colspan=16| nalign=left| BRA LEU,addralign=left| ...if PSR.Z is set, or PSR.C is clear
00110111colspan=16| nalign=left| BRA addralign=left| ...unconditionally
00111000colspan=16| nalign=left| BRA NOV,addralign=left| ...if PSR.V is clear
00111001colspan=16| nalign=left| BRA NC,addralign=left| ...if PSR.C is clear
00111010colspan=16| nalign=left| BRA NZ,addralign=left| ...if PSR.Z is clear
00111011colspan=16| nalign=left| BRA NN,addralign=left| ...if PSR.N is clear
00111100colspan=16| nalign=left| BRA GT,addralign=left| ...if PSR.Z is clear, and PSR.N = PSR.V
00111101colspan=16| nalign=left| BRA GE,addralign=left| ...if PSR.N = PSR.V
00111110colspan=16| nalign=left| BRA GTU,addralign=left| ...if PSR.Z is clear, and PSR.C is set
style="background:lightgrey;"

| 0

0111111colspan=16| ncolspan="5" style="text-align:left;"| (Reserved)
colspan=29|
0 ||colspan=4| opcode ||colspan=4| w || B ||colspan=3| q ||colspan=4| d ||colspan=3| p ||colspan=4| s ||colspan=5| ALU operations: dest ← OP(Ww,source)
01000colspan=4| wBcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| ADD[.B] Ww,src,dstCZNalign=left| dst ← Ww + src
01001colspan=4| wBcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| ADDC[.B] Ww,src,dstCZNalign=left| dst ← Ww + src + C
01010colspan=4| wBcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| SUB[.B] Ww,src,dstCZNalign=left| dst ← Ww − src
01011colspan=4| wBcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| SUBB[.B] Ww,src,dstCZNalign=left| dst ← Ww − ~src − C̅ = Ww + ~src + C
01100colspan=4| wBcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| AND[.B] Ww,src,dstZNalign=left| dst ← Ww & src
01101colspan=4| wBcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| XOR[.B] Ww,src,dstZNalign=left| dst ← Ww ^ src
01110colspan=4| wBcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| IOR[.B] Ww,src,dstZNalign=left| dst ← Ww {{pipe}} src
01111colspan=4| wBcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| MOV[.B] src,dstZNalign=left| dst ← src (offset mode allowed)
colspan=29|
10000colspan=15| fcolspan=4| dalign=left| MOV f,Wdalign=left| Wd ← f
10001colspan=15| fcolspan=4| salign=left| MOV Ws,falign=left| f ← Ws
10010colspan=4| kBcolspan=3| kcolspan=4| dcolspan=3| kcolspan=4| salign=left| MOV[.B] [Ws+s10],Wdalign=left| Load with 10-bit offset
10011colspan=4| kBcolspan=3| kcolspan=4| dcolspan=3| kcolspan=4| salign=left| MOV[.B] Ws,[Wd+s10]align=left| Store with 10-bit offset
colspan=29|
1 || 0 || 1 || 0 || 0 ||colspan=3| opcode ||colspan=4| b || Z || B ||colspan=3| —0— ||colspan=3| p ||colspan=4| s ||colspan=5| Bit operations on source
10100000colspan=4| b0Bcolspan=3 style="background:lightgrey;"| —0—colspan=3| pcolspan=4| salign=left| BSET[.B] #b,srcalign=left| Set bit b of src
10100001colspan=4| b0Bcolspan=3 style="background:lightgrey;"| —0—colspan=3| pcolspan=4| salign=left| BCLR[.B] #b,srcalign=left| Clear bit b of src
10100010colspan=4| b0Bcolspan=3 style="background:lightgrey;"| —0—colspan=3| pcolspan=4| salign=left| BTG[.B] #b,srcalign=left| Toggle bit b of src
10100011colspan=4| b00colspan=3 style="background:lightgrey;"| —0—colspan=3| pcolspan=4| salign=left| BTST.C #b,srcCalign=left| Set PSR.C = bit b of src
10100011colspan=4| b10colspan=3 style="background:lightgrey;"| —0—colspan=3| pcolspan=4| salign=left| BTST.Z #b,srcZalign=left| Set PSR.Z = {{overline|bit b of src}}
10100100colspan=4| bZ0colspan=3 style="background:lightgrey;"| —0—colspan=3| pcolspan=4| salign=left| BTSTS.z #b,srccolspan=2| C/Zalign=left| Test bit b of src (into C or Z), then set
10100101Zcolspan=4| w0colspan=3 style="background:lightgrey;"| —0—colspan=3| pcolspan=4| salign=left| BTST.z Ww,srccolspan=2| C/Zalign=left| Test bit Ww of src
10100110colspan=4| b00colspan=3 style="background:lightgrey;"| —0—colspan=3| pcolspan=4| salign=left| BTSS #b,srcalign=left| Test bit, skip if set
10100111colspan=4| b00colspan=3 style="background:lightgrey;"| —0—colspan=3| pcolspan=4| salign=left| BTS #b,srcalign=left| Test bit, skip if clear
colspan=29|
1 || 0 || 1 || 0 || 1 ||colspan=3| opcode ||colspan=3| b ||colspan=13| f ||colspan=5| Bit operations on f
10101000colspan=3| bcolspan=12| fbalign=left| BSET[.B] f,#balign=left| Set bit b of f
10101001colspan=3| bcolspan=13| falign=left| BCLR.B f,#balign=left| Clear bit b of f
10101010colspan=3| bcolspan=13| falign=left| BTG.B f,#balign=left| Toggle bit b of f
10101011colspan=3| bcolspan=13| falign=left| BTST.B f,#bZalign=left| Test bit b of f
10101100colspan=3| bcolspan=13| falign=left| BTSTS.B f,#bZalign=left| Test bit b of f, then set
10101101Zcolspan=4| w0colspan=3 style="background:lightgrey;"| —0—colspan=3| pcolspan=4| salign=left| BSW.z src,Wwalign=left| Copy PSW.C or {{overline|PSW.Z}} to bit Ww of src
10101110colspan=3| bcolspan=13| falign=left| BTSS f,#balign=left| Test bit, skip if set
10101111colspan=3| bcolspan=13| falign=left| BTSC f,#balign=left| Test bit, skip if clear
colspan=29|
1 || 0 || 1 || 1 || 0 || 0 ||colspan=3| opcode || B ||colspan=10| k ||colspan=4| d ||colspan=5| Register-immediate operations: Wd ← OP(Wd,k)
101100000Bcolspan=10| kcolspan=4| dalign=left| ADD[.B] #u10,WdCZNalign=left| Wd ← Wd + k
101100001Bcolspan=10| kcolspan=4| dalign=left| ADC[.B] #u10,WdCZNalign=left| Wd ← Wd + k + C
101100010Bcolspan=10| kcolspan=4| dalign=left| SUB[.B] #u10,WdCZNalign=left| Wd ← Wd − k
101100011Bcolspan=10| kcolspan=4| dalign=left| SUBB[.B] #u10,WdCZNalign=left| Wd ← Wd − k − C̅
101100100Bcolspan=10| kcolspan=4| dalign=left| AND[.B] #u10,WdZNalign=left| Wd ← Wd & k
101100101Bcolspan=10| kcolspan=4| dalign=left| XOR[.B] #u10,WdZNalign=left| Wd ← Wd ^ k
101100110Bcolspan=10| kcolspan=4| dalign=left| IOR[.B] #u10,WdZNalign=left| Wd ← Wd {{pipe}} k
101100111Bcolspan=10| kcolspan=4| dalign=left| MOV[.B] #u10,Wdalign=left| Wd ← k
colspan=29|
1 || 0 || 1 || 1 || 0 || 1 ||colspan=3| opcode || B || D ||colspan=13| f ||colspan=5| ALU operations: dest ← OP(f,W0)
101101000BDcolspan=13| falign=left| ADD[.B] f[,WREG]CZNalign=left| dest ← f + W0
101101001BDcolspan=13| falign=left| ADC[.B] f[,WREG]CZNalign=left| dest ← f + W0 + C
101101010BDcolspan=13| falign=left| SUB[.B] f[,WREG]CZNalign=left| dest ← f − W0
101101011BDcolspan=13| falign=left| SUBB[.B] f[,WREG]CZNalign=left| dest ← f − W0 + C̅
101101100BDcolspan=13| falign=left| AND[.B] f[,WREG]ZNalign=left| dest ← f & W0
101101101BDcolspan=13| falign=left| XOR[.B] f[,WREG]ZNalign=left| dest ← f ^ W0
101101110BDcolspan=13| falign=left| IOR[.B] f[,WREG]ZNalign=left| dest ← f {{pipe}} W0
101101111B1colspan=13| falign=left| MOV[.B] WREG,falign=left| f ← W0
colspan=29|
1 || 0 || 1 || 1 || 1 || 0 || 0 ||colspan=2| opc ||colspan=4| w ||colspan=3| d || 0 ||colspan=3| p ||colspan=4| s ||colspan=5| 16×16→32 multiplication
101110000colspan=4| wcolspan=3| d0colspan=3| pcolspan=4| salign=left| MUL.UU Ww,src,Wdalign=left| Wd+1:Wd ← Ww × src (unsigned)
101110001colspan=4| wcolspan=3| d0colspan=3| pcolspan=4| salign=left| MUL.US Ww,src,Wdalign=left| Wd+1:Wd ← Ww × src (src signed)
101110010colspan=4| wcolspan=3| d0colspan=3| pcolspan=4| salign=left| MUL.SU Ww,src,Wdalign=left| Wd+1:Wd ← Ww × src (Ww signed)
101110011colspan=4| wcolspan=3| d0colspan=3| pcolspan=4| salign=left| MUL.SS Ww,src,Wdalign=left| Wd+1:Wd ← Ww × src (signed)
colspan=29|
1 || 0 || 1 || 1 || 1 || 0 || 1 ||colspan=2| opc || B ||colspan=3| q ||colspan=4| d ||colspan=3| p ||colspan=4| s ||colspan=5| Program memory access (indirect modes only)
101110100Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| TBLRDL[.B] src,dstalign=left| dst ← ROM[TBLPAG:src] (bits 15:0)
101110101Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| TBLRDH[.B] src,dstalign=left| dst ← ROM[TBLPAG:src] (bits 23:16)
101110110Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| TBLWTL[.B] src,dstalign=left| ROM[TBLPAG:dst] ← src (bits 15:0)
101110111Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| TBLWTH[.B] src,dstalign=left| ROM[TBLPAG:dst] ← src (bits 23:16)
colspan=29|
101111000B0colspan=13| falign=left| MUL[.B] falign=left| W3:W2 ← f × W0 (unsigned)
style="background:lightgrey;"

| 1

01111000B1colspan=13| —style="text-align:left;" colspan="5"| (Reserved)
style="background:lightgrey;"

| 1

01111001colspan=15| —style="text-align:left;" colspan="5"| (Reserved)
style="background:lightgrey;"

| 1

0111101colspan=16| —style="text-align:left;" colspan="5"| (Reserved)
1011111000colspan=3 style="background:lightgrey;"| —0—colspan=3| d0colspan=3| pcolspan=4| salign=left| MOV.D src,Wdalign=left| Load register pair
1011111010colspan=3| qcolspan=4| dcolspan=3 style="background:lightgrey;"| —0—colspan=3| swidth=10pt| 0align=left| MOV.D Ws,dstalign=left| Store register pair
style="background:lightgrey;"

| 1

0111111colspan=16| —style="text-align:left;" colspan="5"| (Reserved)
colspan=29|
1 || 1 || 0 || 0 || 0 ||colspan=3| m || A || S ||colspan=2| x ||colspan=2| y ||colspan=4| i ||colspan=4| j ||colspan=2| a ||colspan=5| DSP MAC (dsPIC only)
colspan=29|
1 || 1 || 0 || 0 || 1 ||colspan=19| ||colspan=5| Other DSP instructions (dsPIC only)
1100111100colspan=3 style="background:lightgrey;"| —0—colspan=4| dcolspan=3| pcolspan=4| salign=left| FF1R src,WdCalign=left| Find first one from right (lsb)
1100111110colspan=3 style="background:lightgrey;"| —0—colspan=4| dcolspan=3| pcolspan=4| salign=left| FF1L src,WdCalign=left| Find first one from left (msb)
colspan=29|
1 || 1 || 0 || 1 || 0 || 0 ||colspan=3| opcode || B ||colspan=3| q ||colspan=4| d ||colspan=3| p ||colspan=4| s ||colspan=5| Shift/rotate general operand
110100000Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| SL[.B] src,dstCZNalign=left| dst ← src << 1, shift left (into carry)
110100010Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| LSR[.B] src,dstCZNalign=left| dst ← src >> 1, logical shift right
110100011Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| ASR[.B] src,dstCZNalign=left| dst ← src >> 1, arithmetic shift right
110100100Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| RLNC[.B] src,dstZNalign=left| dst ← src <<< 1, rotate left (no carry)
110100101Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| RLC[.B] src,dstCZNalign=left| C:dst ← src:C << 1, rotate left through carry
110100110Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| RRNC[.B] src,dstZNalign=left| dst ← src >>> 1, rotate right (no carry)
110100111Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| RRC[.B] src,dstCZNalign=left| dst:C ← C:src >> 1, rotate right through carry
1 || 1 || 0 || 1 || 0 || 1 ||colspan=3| opcode || B || D ||colspan=13| f ||colspan=5| Shift/rotate f
110101000BDcolspan=13| falign=left| SL[.B] f[,WREG]CZNalign=left| dest ← f << 1, shift left (into carry)
110101010BDcolspan=13| falign=left| LSR[.B] f[,WREG]CZNalign=left| dest ← f >> 1, logical shift right
110101011BDcolspan=13| falign=left| ASR[.B] f[,WREG]CZNalign=left| dest ← f >> 1, arithmetic shift right
110101100BDcolspan=13| falign=left| RLNC[.B] f[,WREG]ZNalign=left| dest ← f <<< 1, rotate left (no carry)
110101101BDcolspan=13| falign=left| RLC[.B] f[,WREG]CZNalign=left| C:dest ← f:C << 1, rotate left through carry
110101110BDcolspan=13| falign=left| RRNC[.B] f[,WREG]ZNalign=left| dest ← f >>> 1, rotate right (no carry)
110101111BDcolspan=13| falign=left| RRC[.B] f[,WREG]CZNalign=left| dest:C ← C:f >> 1, rotate right through carry
colspan=29|
1 || 1 || 0 || 1 || 1 || 0 || 0 || 0 || U ||colspan=4| t ||colspan=4| d || D || 0 || 0 ||colspan=4| s ||colspan=5| Divide step (prefix with REPEAT #17)
110110000colspan=4 style="background:lightgrey;"| —0—colspan=4| d000colspan=4| salign=left| DIV.S Wd,WsCZNalign=left| W0 ← Wd/Ws, W1 ← remainder
110110000colspan=4| tcolspan=4| d100colspan=4| salign=left| DIV.SD Wd,WsCZNalign=left| W0 ← Wt:Wd/Ws, W1 ← remainder
110110001colspan=4 style="background:lightgrey;"| —0—colspan=4| d000colspan=4| salign=left| DIV.U Wd,WsCZNalign=left| W0 ← Wd/Ws, W1 ← remainder
110110001colspan=4| tcolspan=4| d100colspan=4| salign=left| DIV.UD Wd,WsCZNalign=left| W0 ← Wt:Wd/Ws, W1 ← remainder
110110010colspan=4| tcolspan=4 style="background:lightgrey;"| —0—000colspan=4| salign=left| DIVF Wt,WsCZNalign=left| W0 ← Wt:0/Ws, W1 ← remainder
style="background:lightgrey;"

| 1

10110011colspan=15| —style="text-align:left;" colspan="5"| (Reserved)
style="background:lightgrey;"

| 1

101101colspan=17| —style="text-align:left;" colspan="5"| (Reserved)
colspan=29|
1 || 1 || 0 || 1 || 1 || 1 ||colspan=3| opcode ||colspan=4| w ||colspan=4| d || i || 0 || 0 ||colspan=4| s ||colspan=5| Shift/rotate multiple
110111000colspan=4| wcolspan=4| d000colspan=4| salign=left| SL Ww,Ws,WdZNalign=left| Wd ← Ww << Ws
110111000colspan=4| wcolspan=4| d100colspan=4| kalign=left| SL Wv,#u4,WdZNalign=left| Wd ← Ww << k
110111100colspan=4| wcolspan=4| d000colspan=4| salign=left| LSR Ww,Ws,WdZNalign=left| Wd ← Ww >> Ws, logical shift right
110111100colspan=4| wcolspan=4| d100colspan=4| kalign=left| LSR Wv,#u4,WdZNalign=left| Wd ← Ww >> k, logical shift right
110111101colspan=4| wcolspan=4| d000colspan=4| salign=left| ASR Ww,Ws,WdZNalign=left| Wd ← Ww >> Ws, arithmetic shift right
110111101colspan=4| wcolspan=4| d100colspan=4| kalign=left| ASR Wv,#u4,WdZNalign=left| Wd ← Ww >> k, arithmetic shift right
110111110colspan=4 style="background:lightgrey;"| —0—colspan=4| dcolspan=3| pcolspan=4| salign=left| FBCL src,WdCalign=left| Find permissible arithmetic normalization shift
colspan=29|
111000000colspan=4 style="background:lightgrey;"| —0—B000colspan=3| pcolspan=4| salign=left| CP0[.B] srcCZNalign=left| Compare with zero, src − 0
111000010colspan=4| wB000colspan=3| pcolspan=4| salign=left| CP[.B] Ww,srcCZNalign=left| Compare, Ww − src (Ww + ~src + 1)
111000011colspan=4| wB000colspan=3| pcolspan=4| salign=left| CPB[.B] Ww,srcCZNalign=left| Compare with borrow, Ww − src − C̅ (Ww + ~src + C)
111000100B0colspan=13| falign=left| CP0[.B] fCZNalign=left| Compare with zero, f − 0
111000110B0colspan=13| falign=left| CP[.B] fCZNalign=left| Compare, f − W0
111000111B0colspan=13| falign=left| CPB[.B] fCZNalign=left| Compare with borrow, f − W0 − C̅ (f + ~W0 + C)
style="background:lightgrey;"

| 1

110010colspan=17| —colspan="5" style="text-align:left;"| (Reserved)
colspan=29|
1 || 1 || 1 || 0 || 0 || 1 || 1 ||colspan=2| opc ||colspan=4| w || B ||colspan=6| —0— ||colspan=4| s ||colspan=5| Compare and skip
111001100colspan=4| wBcolspan=6 style="background:lightgrey;"| —0—colspan=4| salign=left| CPSGT[.B] Ww,Wsalign=left| ...if Ww > Ws, signed
111001101colspan=4| wBcolspan=6 style="background:lightgrey;"| —0—colspan=4| salign=left| CPSLT[.B] Ww,Wsalign=left| ...if Ww < Ws, signed
111001110colspan=4| wBcolspan=6 style="background:lightgrey;"| —0—colspan=4| salign=left| CPSNE[.B] Ww,Wsalign=left| ...if Ww ≠ Ws
111001111colspan=4| wBcolspan=6 style="background:lightgrey;"| —0—colspan=4| salign=left| CPSNE[.B] Ww,Wsalign=left| ...if Ww = Ws
colspan=29|
111010000Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| INC[.B] src,dstCZNalign=left| dst ← src+1
111010001Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| INC2[.B] src,dstCZNalign=left| dst ← src+2
111010010Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| DEC[.B] src,dstCZNalign=left| dst ← src−1
111010011Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| DEC2[.B] src,dstCZNalign=left| dst ← src−2
111010100Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| NEG[.B] src,dstCZNalign=left| dst ← ~src+1
111010101Bcolspan=3| qcolspan=4| dcolspan=3| pcolspan=4| salign=left| COM[.B] src,dstZNalign=left| dst ← ~src
111010110Bcolspan=3| qcolspan=4| dcolspan=7 style="background:lightgrey;"| —0—align=left| CLR[.B] dstalign=left| dst ← 0
111010111Bcolspan=3| qcolspan=4| dcolspan=7 style="background:lightgrey;"| —0—align=left| SETM[.B] dstalign=left| dst ← ~0
111011000BDcolspan=13| falign=left| INC[.B] f[,WREG]CZNalign=left| dest ← f+1
111011001BDcolspan=13| falign=left| INC2[.B] f[,WREG]CZNalign=left| dest ← f+2
111011010BDcolspan=13| falign=left| DEC[.B] f[,WREG]CZNalign=left| dest ← f−1
111011011BDcolspan=13| falign=left| DEC[.B] f[,WREG]CZNalign=left| dest ← f−2
111011100BDcolspan=13| falign=left| NEG[.B] f[,WREG]CZNalign=left| dest ← ~f+1
111011101BDcolspan=13| falign=left| COM[.B] f[,WREG]ZNalign=left| dest ← ~f
111011110BDcolspan=13| falign=left| CLR[.B] f[,WREG]align=left| dest ← 0
111011111BDcolspan=13| falign=left| SETM[.B] f[,WREG]align=left| dest ← ~0
colspan=29|
1 || 1 || 1 || 1 || 0 || 0 ||colspan=2| m || A || 1 ||colspan=2| x ||colspan=2| y ||colspan=4| i ||colspan=4| j ||colspan=2| opc ||colspan=5| DSP MPY/MAC/ED/EDAC (dsPIC only)
style="background:lightgrey;"

| 1

11101colspan=18| —colspan="5" style="text-align:left;"| (Reserved)
colspan=29|
11111000colspan=15| f0align=left| PUSH falign=left| Push f on top of stack
11111001colspan=15| f0align=left| POP falign=left| Pop f from top of stack
1111101000colspan=14| kalign=left| LNK #u14align=left| Push W14, W14 ← W15, W15 += k
1111101010colspan=14 style="background:lightgrey;"| —0—align=left| ULNKalign=left| W15 ← W14, pop W14
1111101100colspan=3| 000colspan=4| dcolspan=3| pcolspan=4| salign=left| SE src,dstCZNalign=left| dst ← sign_extend(src), copy bit 7 to bits 15:8
1111101110colspan=3| 000colspan=4| dcolspan=3| pcolspan=4| salign=left| ZE src,dst1Z0align=left| dst ← zero_extend(src), clear bits 15:8
1111110000colspan=14| kalign=left| DISI #u14align=left| Disable interrupt for k+1 cycles
1111110100colspan=3| 000colspan=4| dcolspan=3| 000colspan=4| salign=left| EXCH Ws,Wdalign=left| Swap contents of registers Ws, Wd
1111110101colspan=3| 000colspan=4| 0000colspan=3| 000colspan=4| salign=left| DAW.B WsCalign=left| Decimal adjust based on C, DC
111111011Bcolspan=3| 000colspan=4| 0000colspan=3| 000colspan=4| salign=left| SWAP[.B] Wsalign=left| Swap halves of Ws
1111111000colspan=14 style="background:lightgrey;"| —0—align=left| RESETalign=left| Software reset
11111110010colspan=12 style="background:lightgrey;"| —0—kalign=left| PWRSAV #u1align=left| Go into sleep or idle mode
11111110011colspan=13 style="background:lightgrey;"| —0—align=left| CLRWDTalign=left| Clear watchdog timer
11111110100colspan=13 style="background:lightgrey;"| —0—align=left| POP.Salign=left| Pop shadow registers (W0–3, part of PSR)
11111110101colspan=13 style="background:lightgrey;"| —0—align=left| PUSH.Salign=left| Push shadow registers (W0–3, part of PSR)
style="background:lightgrey;"

| 1

111111011colspan=14| —style="text-align:left;" colspan="5"| (Reserved)
11111111colspan=16 style="background:lightgrey;"| —align=left| NOPRalign=left| No operation (version #2)

References

{{Microchip Technology}}

Category:Microcontrollers

Category:Instruction set listings