PWRficient

The PA6T is the first and only processor core from P.A. Semi, in two distinct product lines: 16xxM dual core and 13xxM/E single core. The PA6T lines differed in L2 cache size, memory controllers, communication functionality, and cryptography offloading features. P.A. Semi planned up to 16 cores.{{cite web

|title=PA Semi heads to 16 cores on back of $50m boost

|publisher=The Register

|url=https://www.theregister.co.uk/2006/05/17/pasemi_core_ti/

|date=2006-05-17

|accessdate=2012-07-02

}}

The PA6T is the first Power ISA core designed from scratch in the previous ten years outside the AIM alliance, which included IBM, Motorola, Freescale, and Apple Inc. Since Texas Instruments was an investors in P.A. Semi, it was suggested that its fabrication plants would have manufactured the PWRficient processors.

PWRficient processors were initially shipped to select customers in February 2007 and were released worldwide in Q4 2007.{{cite web|title=Press release |publisher=P.A. Semi |url=http://pasemi.com/news/pr_2007_02_05b.html |accessdate=2007-02-07 |url-status=dead |archiveurl=https://web.archive.org/web/20070821022643/http://pasemi.com/news/pr_2007_02_05b.html |archivedate=August 21, 2007 }}

P.A. Semi was bought by Apple Inc. in April 2008,{{cite news

|title=Apple Buys Chip Designer

|work=Forbes

|url=https://www.forbes.com/2008/04/23/apple-buys-pasemi-tech-ebiz-cz_eb_0422apple.html

|date=2008-04-23

|accessdate=2011-07-05

|first1=Erika

|last1=Brown

|first2=Elizabeth

|last2=Corcoran

|first3=Brian

|last3=Caulfield

}} and closed development of PWRficient architecture processors. However, it will continue to manufacture, sell, and support these components for the foreseeable future due to an agreement with the US Government for some military applications.{{cite web

|title=Apple will please missile makers by backing PA Semi's chip

|publisher=The Register

|url=https://www.theregister.co.uk/2008/05/16/pasemi_apple_support/

|date=2008-05-16

|accessdate=2011-07-05

}}{{cite web

|title=DoD may push back on Apple's P.A. Semi bid

|publisher=EETimes

|url=http://www.eetimes.com/electronics-news/4076837/DoD-may-push-back-on-Apple-s-P-A-Semi-bid

|date=2008-05-23

|accessdate=2011-07-05

|archive-url=https://web.archive.org/web/20101213053945/http://www.eetimes.com/electronics-news/4076837/DoD-may-push-back-on-Apple-s-P-A-Semi-bid

|archive-date=2010-12-13

|url-status=dead

}} Some components of the P.A. Semi PWRficient were later integrated into Apple silicon.{{Cite web|url=https://lore.kernel.org/linuxppc-dev/YWQMSG0U1Ae4pTCD@kunai/T/|title = [PATCH v2 00/11] Add Apple M1 support to PASemi i2c driver}}

{{Infobox CPU

| name = PA6T-1682M

| image = Pwrficient.png

| image_size = 150

| caption =

| produced-start = 2007

| produced-end = 2008

| slowest = 1.8 | slow-unit = GHz

| fastest = 2.0 | fast-unit = GHz

| fsb-slowest =

| fsb-fastest =

| fsb-slow-unit =

| fsb-fast-unit =

| hypertransport-slowest =

| hypertransport-fastest =

| hypertransport-slow-unit =

| hypertransport-fast-unit =

| size-from = 65 nm

| size-to =

| soldby =

| designfirm = P.A. Semi

| manuf1 =

| core1 =

| sock1 =

| pack1 =

| brand1 =

| arch = Power ISA (Power ISA v.2.04)

| microarch = PA6T

| cpuid =

| code =

| numcores = 2

| l1cache = 64+64 KB/core

| l2cache = 2 MB/core

| l3cache =

| predecessor =

| application =

}}

PWRficient processors comprise three parts:

PA6T

• Superscalar, out-of-order 32-bit/64-bit Power ISA processor core
• Adheres to the Power ISA v.2.04
• Little endian or big endian operation
• 64/64 kB instruction and data L1 caches. 32 GB/s bandwidth.
• Six execution units including a double precision FPU and AltiVec unit
• Hypervisor and virtualization support
• Maximum 7 W at 2 GHz
• 11 million transistors, 10 mm² large @ 65 nm.

CONEXIUM

• scalable cross-bar interconnect
• 1–8 SMP cores
• 1–2 L2 caches, 512 KB – 8 MB large. 16 GB/s bandwidth.
• 1–4 1067 MHz DDR2 memory controllers. 16 GB/s bandwidth.
• 64 GB/s peak bandwidth
• MOESI coherency

ENVOI

• Centralized DMA engine, 32 GB/s bandwidth
• 16–64 SerDes lanes
• XAUI
• PCI Express
• SGMII
• Offload engine for cryptography, RAID, TCP

• Curtiss-Wright planned the 1682M processor for its signal processing systems.http://pasemi.com/news/pr_2007_12_20a.html {{Dead link|date=February 2011}}
• Mercury Computer Systems planned the 1682M processor for its signal and image processing systems.{{cite web | date=June 7, 2007 | title=Mercury Computer Systems and P.A. Semi Collaborate to Bring PWRficient Processor to Signal and Image Processing Applications | url=https://vita.mil-embedded.com/news/mercury-processor-signal-image-processing-applications/ | access-date=August 18, 2022}}
• NEC planned the 1682M processor for its storage array systems.{{Cite web|url=https://www.theregister.co.uk/2008/01/14/pasemi_takes_nec/|title = NEC pops PA Semi chips into storage gear|website = The Register}}
• AmigaOne X1000 has the 1682M processor as CPU.{{Cite web |url=http://a-eon.com/x1000.html |title=X1000 |access-date=2011-07-05 |archive-url=https://web.archive.org/web/20110707072105/http://a-eon.com/x1000.html |archive-date=2011-07-07 |url-status=dead }}

{{reflist}}

• {{Cite web |url=http://news.com.com/Start-up+plans+new+energy-efficient+processor/2100-1006_3-5907281.html |title=Start-up plans new energy-efficient processor |access-date=2006-11-24 |archive-url=https://archive.today/20130102093013/http://news.com.com/Start-up+plans+new+energy-efficient+processor/2100-1006_3-5907281.html |archive-date=2013-01-02 |url-status=bot: unknown }}
• [http://www.electronicsweekly.com/Articles/2005/10/24/36730/PASemiattacksperformanceWatt.htm PA Semi attacks performance/Watt]
• [http://www.realworldtech.com/page.cfm?ArticleID=RWT102405055354 FPF 2005: P.A. Semi's PA6T-1682M System on a Chip – Real World Technologies]
• [https://archive.today/20110811013157/http://www.elecdesign.com/Articles/Index.cfm?AD=1&AD=1&AD=1&ArticleID=15356 Judicious Clocking Subdues Power-Architecture Cooling Needs – Electronic Design]

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Category:Power microprocessors