Princeton Application Repository for Shared-Memory Computers

The introduction of chip-multiprocessors required computer manufacturers to rewrite software for the first time to take advantage of parallel processing capabilities, including rewriting existing systems for testing and development.{{Citation

|last1=Rabaey

|first1=Jan M.

|last2=Burke

|first2=Daniel

|last3=Lutz

|first3=Ken

|last4=Wawrzynek

|first4=John

|contribution=Workloads of the Future

|contribution-url=http://www2.computer.org/cms/Computer.org/ComputingNow/homepage/0908/WorkloadsoftheFuture.pdf

|title=IEEE Design & Test of Computers

|publisher=IEEE

|date=July–August 2008

|access-date=2010-02-12

|archive-date=2011-08-07

|archive-url=https://web.archive.org/web/20110807224952/http://www2.computer.org/cms/Computer.org/ComputingNow/homepage/0908/WorkloadsoftheFuture.pdf

|url-status=dead

}} At that time parallel software only existed in very specialized areas. However, before chip-multiprocessors became commonly available software developers were not willing to rewrite any mainstream programs, which means hardware manufacturers did not have access to any programs for test and development purposes that represented the expected real-world program behavior accurately. This posed a hen-and-egg problem that motivated a new type of benchmark suite with parallel programs that could take full advantage of chip-multiprocessors.

PARSEC was created to break this circular dependency. It was designed to fulfill the following five objectives:{{Citation

|last1=Bienia|first1=Christian

|last2=Kumar|first2=Sanjeev

|last3=Singh|first3=Jaswinder Pal

|last4=Li|first4=Kai

|contribution=The PARSEC Benchmark Suite: Characterization and Architectural Implications

|contribution-url=http://portal.acm.org/citation.cfm?id=1454128

|title=Proceedings of the 17th international conference on Parallel architectures and compilation techniques

|publisher=Association for Computing Machinery, New York, NY, USA

|date=October 2008

}}

1. Focuses on multithreaded applications
2. Includes emerging workloads
3. Has a diverse selection of programs
4. Workloads employ state-of-art techniques
5. The suite supports research

Traditional benchmarks that were publicly available before PARSEC were generally limited in their scope of included application domains or typically only available in an unparallelized, serial version. Parallel programs were only prevalent in the domain of High-Performance Computing and on a much smaller scale in business environments.{{Cite book | last1 = Bienia | first1 = C. | last2 = Kumar | first2 = S. | last3 = Kai Li | doi = 10.1109/IISWC.2008.4636090 | chapter = PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors | title = 2008 IEEE International Symposium on Workload Characterization | pages = 47 | year = 2008 | isbn = 978-1-4244-2777-2 | s2cid = 1805881 }} Chip-multiprocessors however were expected to be heavily used in all areas of computing such as with parallelized consumer applications.

The PARSEC Benchmark Suite is available in version 2.1, which includes the following workloads:{{Citation

|last1=Bienia|first1=Christian

|last2=Li|first2=Kai

|contribution=PARSEC 2.0: A New Benchmark Suite for Chip-Multiprocessors

|contribution-url=http://www-mount.ece.umn.edu/~jjyi/MoBS/2009/MoBS_2009_Advance_Program.html

|title=Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation

|publisher=Association for Computing Machinery, New York, NY, USA

|date=June 2009

}}

• Blackscholes
• Bodytrack
• Canneal
• Dedup
• Facesim
• Ferret
• Fluidanimate
• Freqmine
• Raytrace
• Streamcluster
• Swaptions
• Vips
• X264

{{Reflist}}

• [http://parsec.cs.princeton.edu/ The PARSEC Benchmark Suite]
• [http://wiki.cs.princeton.edu/index.php/PARSEC The PARSEC Wiki]

Category:Benchmarks (computing)

Category:Evaluation of computers