Programmable metallization cell

PMC is a two terminal resistive memory technology developed at Arizona State University. PMC is an electrochemical metallization memory that relies on redox reactions to form and dissolve a conductive filament.{{cite journal|last1=Valov|first1=Ilia|last2=Waser|first2=Rainer|last3=Jameson|first3=John|last4=Kozicki|first4=Michael|title=Electrochemical metallization memories-fundamentals, applications, prospects|journal=Nanotechnology|date=June 2011|volume=22|issue=25|page=254003|doi=10.1088/0957-4484/22/25/254003|pmid=21572191|bibcode=2011Nanot..22y4003V|s2cid=250920840 |url=https://patents.google.com/patent/US10833264B2/en }} The state of the device is determined by the resistance across the two terminals. The existence of a filament between the terminals produces a low resistance state (LRS) while the absence of a filament results in a high resistance state (HRS). A PMC device is made of two solid metal electrodes, one relatively inert (e.g., tungsten or nickel) the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between them.{{Cite book |author= Michael N. Kozicki |author2= Chakravarthy Gopalan |author3= Murali Balakrishnan |author4= Mira Park |author5= Maria Mitkova |title= Proceedings. 2004 IEEE Computational Systems Bioinformatics Conference |chapter= Nonvolatile memory based on solid electrolytes |date= August 20, 2004 |pages= 10–17 |publisher= IEEE |chapter-url= http://www.axontc.com/images/Nov04NVMTSpaper.pdf |access-date= April 13, 2017 |doi= 10.1109/NVMT.2004.1380792 |isbn= 0-7803-8726-0 |s2cid= 2884270 |archive-date= July 11, 2016 |archive-url= https://web.archive.org/web/20160711195216/http://axontc.com/images/Nov04NVMTSpaper.pdf |url-status= dead }}

The resistance state of a PMC is controlled by the formation (programming) or dissolution (erasing) of a metallic conductive filament between the two terminals of the cell. A formed filament is a fractal tree like structure.

PMC rely on the formation of a metallic conductive filament to transition to a low resistance state (LRS). The filament is created by applying a positive voltage bias (V) to the anode contact (active metal) while grounding the cathode contact (inert metal). The positive bias oxidizes the active metal (M):

:M → M⁺ + e⁻

The applied bias generates an electric field between the two metal contacts. The ionized (oxidized) metal ions migrate along the electric field toward the cathode contact. At the cathode contact, the metal ions are reduced:

:M⁺ + e⁻ → M

As the active metal deposits on the cathode, the electric field increases between the anode and the deposit. The evolution of the local electric field (E) between the growing filament and the anode can be simplistically related to the following:

:$E\; =\; -\backslash frac\{V\}\{d\}$

where d is the distance between the anode and the top of the growing filament. The filament will grow to connect to the anode within a few nanoseconds. Metal ions will continue to be reduced at the filament until the voltage is removed, broadening the conductive filament and decreasing the resistance of the connection over time. Once the voltage is removed, the conductive filament will remain, leaving the device in a LRS.

The conductive filament may not be continuous, but a chain of electrodeposit islands or nanocrystals.{{Cite book |date= November 2006 |pages= 111–115 |author1=Muralikrishnan Balakrishnan |author2=Sarath Chandran Puthen Thermadam |author3=Maria Mitkova |author4=Michael N. Kozicki |title= 2006 7th Annual Non-Volatile Memory Technology Symposium |chapter= A Low Power Non-Volatile Memory Element Based on Copper in Deposited Silicon Oxide |publisher= IEEE |doi= 10.1109/NVMT.2006.378887 |isbn= 0-7803-9738-X |s2cid= 27573769 }} This is likely to prevail at low programming currents (less than 1 μA) whereas higher programming current will lead to a mostly metallic conductor.

A PMC can be "erased" into a high resistance state (HRS) by applying a negative voltage bias to the anode. The redox process used to create the conductive filament is reversed and the metal ions migrate along the reversed electric field to reduce at the anode contact. With the filament removed, the PMC is analogous to parallel plate capacitor with a high resistance of several MΩ to GΩ between the contacts.

An individual PMC can be read by applying a small voltage across the cell. As long as the applied read voltage is less than both the programming and erasing voltage threshold, the direction of the bias is not significant.

CBRAM differs from metal-oxide ReRAM in that for CBRAM metal ions dissolve readily in the material between the two electrodes, while for metal-oxides, the material between the electrodes requires a high electric field causing local damage akin to dielectric breakdown, producing a trail of conducting defects (sometimes called a "filament"). Hence for CBRAM, one electrode must provide the dissolving ions, while for metal-oxide RRAM, a one-time "forming" step is required to generate the local damage.

The primary form of solid-state non-volatile memory in use is flash memory, which is finding use in most roles formerly filled by hard drives. Flash, however, has problems that led to many efforts to introduce products to replace it.

Flash is based on the floating gate concept, essentially a modified transistor. Conventional flash transistors have three connections, the source, drain and gate. The gate is the essential component of the transistor, controlling the resistance between the source and drain, and thereby acting as a switch. In the floating gate transistor, the gate is attached to a layer that traps electrons, leaving it switched on (or off) for extended periods of time. The floating gate can be re-written by passing a large current through the emitter-collector circuit.

It is this large current that is flash's primary drawback, and for a number of reasons. For one, each application of the current physically degrades the cell, such that the cell will eventually be unwritable. Write cycles on the order of 10⁵ to 10⁶ are typical, limiting flash applications to roles where constant writing is not common. The current also requires an external circuit to generate, using a system known as a charge pump. The pump requires a fairly lengthy charging process so that writing is much slower than reading; the pump also requires much more power. Flash is thus an "asymmetrical" system, much more so than conventional RAM or hard drives.

Another problem with flash is that the floating gate suffers leakage that slowly releases the charge. This is countered through the use of powerful surrounding insulators, but these require a certain physical size in order to be useful and also require a specific physical layout, which is different from the more typical CMOS layouts, which required several new fabrication techniques to be introduced. As flash scales rapidly downward in size the charge leakage increasingly becomes a problem, which led to predictions of its demise. However, massive market investment drove development of flash at rates in excess of Moore's Law, and semiconductor fabrication plants using 30 nm processes were brought online in late 2007.

In contrast to flash, PMC writes with relatively low power and at high speed. The speed is inversely related to the power applied (to a point, there are mechanical limits), so the performance can be tuned.

PMC, in theory, can scale to sizes much smaller than flash, theoretically as small as a few ion widths wide. Copper ions are about 0.75 angstroms,{{Cite web |url=http://www.astro.lsa.umich.edu/~cowley/ionsize.html |title=Ion Sizes of Common Elements |archive-url=https://web.archive.org/web/20071107171039/http://www.astro.lsa.umich.edu/~cowley/ionsize.html |archive-date=2007-11-07 }}, compare with Co so line widths on the order of nanometers seem possible. PMC was promoted as simpler in layout than flash.

PMC technology was developed by Michael Kozicki, professor of electrical engineering at Arizona State University in the 1990s.{{Cite web|url=https://patents.google.com/patent/US5761115/en|title=Programmable metallization cell structure and method of making same}}{{Cite web|url=https://patents.google.com/patent/US6418049/en|title=Programmable sub-surface aggregating metallization structure and method of making same}}{{Cite web|url=https://patents.google.com/patent/US6487106/en|title=Programmable microelectronic devices and method of forming and programming same}}{{Cite web|url=https://patents.google.com/patent/US7132675/en|title=Programmable conductor memory cell structure and method therefor}}[https://patents.google.com/patent/US7372065 U.S. Patent 7,372,065]{{Cite web|url=https://patents.google.com/patent/US7728322/en|title=Programmable metallization cell structures including an oxide electrolyte, devices including the structure and method of forming same}}{{Cite book |volume= 3 |pages= 33–36 |date= May 1998 |author=B. Swaroop |author2=W. C. West |author3=G. Martinez |author4=Michael N. Kozicki |author5=L.A. Akers |title= ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187) |chapter= Programmable current mode Hebbian learning neural network using programmable metallization cell |publisher= IEEE |doi= 10.1109/ISCAS.1998.703888 |isbn= 0-7803-4455-3 |s2cid= 61167613 }}

Early experimental PMC systems were based on silver-doped germanium selenide glasses. Work turned to silver-doped germanium sulfide electrolytes and then to the copper-doped germanium sulfide electrolytes.{{Cite book |pages= 83–89 |publisher= IEEE |author=M.N. Kozicki |author2=M. Balakrishnan |author3=C. Gopalan |author4=C. Ratnakumar |author5=M. Mitkova |title= Symposium Non-Volatile Memory Technology 2005 |chapter= Programmable metallization cell memory based on Ag-Ge-S and Cu-Ge-S solid electrolytes |date= November 2005 |doi= 10.1109/NVMT.2005.1541405 |isbn= 0-7803-9408-9 |s2cid= 45696302 }} There has been renewed interest in silver-doped germanium selenide devices due to their high, high resistance state. Copper-doped silicon dioxide glass PMC would be compatible with the CMOS fabrication process.

In 1996, Axon Technologies was founded to commercialize the PMC technology.

Micron Technology announced work with PMC in 2002.{{Cite news |title= Micron Technology Licenses Axon's Programmable Metallization Cell Technology |work= Press release |date= January 18, 2002 }} Infineon followed in 2004.{{Cite web|url=https://www.design-reuse.com/news/8739/axon-infineon-licensee-programmable-metallization-cell-nonvolatile-memory-technology.html|title=Axon Technologies Corp. Announces Infineon as New Licensee of Programmable Metallization Cell Nonvolatile Memory Technology|website=Design And Reuse}} PMC technology was licensed to Adesto Technologies by 2007.{{cite magazine |url= https://www.wired.com/gadgets/miscellaneous/news/2007/10/ion_memory |title=Terabyte Thumb Drives Made Possible by Nanotech Memory |first=Alexis |last=Madrigal |date= October 26, 2007 |magazine=Wired |archive-date= May 11, 2008 |archive-url= https://web.archive.org/web/20080511175927/http://www.wired.com/gadgets/miscellaneous/news/2007/10/ion_memory |access-date= April 13, 2017 }}

infineon had spun off memory business to its Qimonda company, which in turn sold it to Adesto Technologies. A DARPA grant was awarded in 2010 for further research.{{Cite news |title= Adesto Technologies Wins DARPA Award to Develop Sub-Threshold Non-Volatile, Embedded CBRAM Memory |work= Press release |date= November 29, 2010 |publisher= Adesto |url= http://www.adestotech.com/news-detail/adesto-technologies-wins-darpa-award-to-develop-sub-threshold-non-volatile-embedded-cbram-memory/ |access-date= April 13, 2017 }}

In 2011, Adesto Technologies allied with the French company Altis Semiconductor for development and manufacturing of CBRAM.[http://www.altissemiconductor.com/fr/index.php/la-societe/media-center/communiques-presse-menu/archive-press-menu/139-altis-and-adesto-cbram Altis et Adesto Technologies annoncent un partenariat sur les technologies Mémoires CBRAM avancées – Business Wire – published 27 June 2011 - viewed 28 March 2014] {{webarchive|url=https://web.archive.org/web/20140331150830/http://www.altissemiconductor.com/fr/index.php/la-societe/media-center/communiques-presse-menu/archive-press-menu/139-altis-and-adesto-cbram |date=31 March 2014 }} In 2013, Adesto introduced a sample CBRAM product in which a 1 megabit part was promoted to replace EEPROM.{{Cite news |title= Adesto's CBRAM targets 70 billion dollar market |work= Nanalyze |date= July 30, 2013 |url= http://www.nanalyze.com/2013/07/adesto-cbram-targets-70-billion-dollar-market |access-date= April 13, 2017 }}

NEC developed the so-called nanobridge technology, using Cu₂S or tantalumpentoxide as dielectric material. Hereby copper (compatible with copper metallization of the IC) makes the copper to migrate through Cu₂S or Ta₂O₅ making or breaking shorts between the copper and ruthenium electrodes.{{cite journal|last1=Sakamoto|first1=Toshitsugu|last2=Banno|first2=Naoki|last3=Iguchi|first3=Noriyuki|last4=Kawaura|first4=Hisao|last5=Sunamura|first5=Hiroshi|last6=Fujieda|first6=Shinji|last7=Terabe|first7=Kazuya|last8=Hasegawa|first8=Tsuyoshi|last9=Aono|first9=Masakazu|title=A Ta₂O₅ solid-electrolyte switch with improved reliability|year=2007|pages=38–39|doi=10.1109/VLSIT.2007.4339718|s2cid=38195904 }}{{Cite web |url=https://www.eetimes.com/nec-nanobridge-could-build-programmable-ics/# |title=NEC: Nanobridge could build programmable ICs |date=23 February 2004 |access-date=2020-10-22}}{{Cite web |url=https://www.tia-nano.jp/data/doc/1515026501_doc_13_1.pdf |title=Low-power FPGA based on NanoBridge®technology |access-date=2020-10-22}}{{Cite web|url=https://patents.google.com/patent/US20130181180/en|title=Semiconductor device}}

The dominant use of this type of memory are space applications, since this type of memory is intrinsically radiation hard.

• Static random-access memory

{{Reflist}}

• [https://web.archive.org/web/20071031031203/http://www.axontc.com/ Axon Technologies Corporation]
• [http://kozicki.faculty.asu.edu/ Michael N. Kozicki]
• [http://www.adestotech.com/ Adesto Technologies]

{{emerging technologies|topics=yes|infocom=yes}}

Category:Computer memory

Category:Non-volatile memory