RISC-V instruction listings

The RISC-V instruction set refers to the set of instructions that RISC-V compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.

RISC-V Integer Instructions

The table below contains a list of the RV Integer Instructions.{{cite web |title=The RISC-V Instruction Set Manual Volume I |url=https://drive.google.com/file/d/1uviu1nH-tScFfgrovvFCrj7Omv8tFtkp/view |publisher=RISC-V |access-date=4 February 2025 |format=PDF |date=11 April 2024}} The integer instruction set is divided in the base I part of the ISA that comes in a 32 bit RV32 and 64 bit RV64 version and M, B and Zicond extensions. There is also an A extension for atomic instructions and F and D instructions for floating point operations.

Instruction	Name	Format	Extension	RV64
class="wikitable" \|+ RV Integer (pseudo) Instructions
{{Mono\|lb}}	Load Byte	rd, imm12(rs)	I
{{Mono\|lh}}	Load Half	rd, imm12(rs)	I
{{Mono\|lw}}	Load Word	rd, imm12(rs)	I
{{Mono\|ld}}	Load Double	rd, imm12(rs)	I	x
{{Mono\|lbu}}	Load Byte (U)	rd, imm12(rs)	I
{{Mono\|lhu}}	Load Half (U)	rd, imm12(rs)	I
{{Mono\|lwu}}	Load Word (U)	rd, imm12(rs)	I	x
colspan="5" \|
{{Mono\|sb}}	Store Byte	rs1, imm12(rs2)	I
{{Mono\|sh}}	Store Half	rs1, imm12(rs2)	I
{{Mono\|sw}}	Store Word	rs1, imm12(rs2)	I
{{Mono\|sd}}	Store Double	rs1, imm12(rs2)	I	x
colspan="5" \|
{{Mono\|li}}	Load Immediate	rd, imm	IAssembler macro, for immediates needing less than 12 bit expands to addi rd zero imm
{{Mono\|lui}}	Load Upper Immediate	rd, imm20	I
{{Mono\|auipc}}	Add Upper Immediate to Program Counter	rd, imm20	I
colspan="5" \|
{{Mono\|mv}}	MoVe	rd, rs	IPseudo Instruction. Expands to single instruction.
{{Mono\|sext.b}}	move Sign EXTended least significant Byte	rd, rs	B
{{Mono\|sext.h}}	move Sign Extended least significant Half	rd, rs	B
{{Mono\|sext.w}}	move Sign EXTended least significant Word	rd, rs	I	x
{{Mono\|zext.b}}	move Zero EXTended least significant Byte	rd, rs	I
{{Mono\|zext.h}}	move Zero EXTended least significant Half	rd, rs	B
{{Mono\|zext.w}}	move Zero EXTended least significant Word	rd, rs	B	x
{{Mono\|rev8}}	move with REVersed byte order	rd, rs	B
{{Mono\|czero.eqz}}	move Conditional on EQual to Zero or ZERO	rd, rs1, rs2	Zicond
{{Mono\|czero.nez}}	move Conditional on Not Equal to Zero or ZERO	rd, rs1, rs2	Zicond
colspan="5" \|
{{Mono\|addi}}	ADD Immediate	rd, rs, imm12	I
{{Mono\|add}}	ADD	rd, rs1, rs2	I
{{Mono\|sh1add}}	SHift1 ADD	rd, rs1, rs2	B
{{Mono\|sh2add}}	SHift2 ADD	rd, rs1, rs2	B
{{Mono\|sh3add}}	SHift3 ADD	rd, rs1, rs2	B
{{Mono\|add.wu}}	ADD Word(U to double)	rd, rs1, rs2	B	x
{{Mono\|sh1add.wu}}	SHift1 Word(U in double) Add to double	rd, rs1, rs2	B	x
{{Mono\|sh2add.wu}}	SHift2 Word(U in double) Add to double	rd, rs1, rs2	B	x
{{Mono\|sh3add.wu}}	SHift3 Word(U in double) Add to double	rd, rs1, rs2	B	x
{{Mono\|addiw}}	ADD Word to Word Immediate	rd, rs, imm12	I	x
{{Mono\|addw}}	ADD Word	rd, rs1, rs2	I	x
{{Mono\|sub}}	SUBtract	rd, rs1, rs2	I
{{Mono\|subw}}	SUBtract Word	rd, rs1, rs2	I	x
{{mono\|neg}}	NEGative.	rd, rs	I
{{mono\|negw}}	Negative Word	rd, rs	I	x
colspan="5" \|
{{Mono\|mul}}	MULtiply	rd, rs1, rs2	M
{{Mono\|mulw}}	MULtiply Word	rd, rs1, rs2	M	x
{{Mono\|mulh}}	MULtiply High part	rd, rs1, rs2	M
{{Mono\|mulhu}}	MULtiply High Part Unsigned	rd, rs1, rs2	M
{{Mono\|mulhsu}}	MULtiply High Part Unsigned Signed	rd, rs1, rs2	M
{{Mono\|div}}	DIVide	rd, rs1, rs2	M
{{Mono\|divu}}	DIVide (U)	rd, rs1, rs2	M
{{Mono\|rem}}	REMainder	rd, rs1, rs2	M
{{Mono\|remu}}	REMainder (U)	rd, rs1, rs2	M
colspan="5" \|
{{Mono\|min}}	MINimum	rd, rs1, rs2	B
{{Mono\|max}}	MAXimum	rd, rs1, rs2	B
{{Mono\|minu}}	MINimum (U)	rd, rs1, rs2	B
{{Mono\|maxu}}	MAXimum (U)	rd, rs1, rs2	B
colspan="5" \|
{{Mono\|seqz}}	Set EQual to Zero	rd, rs	I
{{Mono\|snez}}	Set Not Equal to Zero	rd, rs	I
{{Mono\|slti}}	Set Less Than Immediate	rd, rs, imm12	I
{{Mono\|slt}}	Set Less Than	rd, rs1, rs2	I
{{Mono\|sltiu}}	Set Less Than Immediate (U)	rd, rs, imm12	I
{{Mono\|sltu}}	Set Less Than (U)	rd, rs1, rs2	I
{{Mono \|bexti}}	Bit Extract Immediate	rd, rs, imm5/6	B
{{Mono\|bext}}	Bit Extract	rd, rs1, rs2	B
colspan="5" \|
{{Mono\|andi}}	AND Immediate	rd, rs, imm12	I
{{Mono\|and}}	AND	rd, rs1, rs2	I
{{Mono\|andn}}	AND Not	rd, rs1, rs2	B
{{Mono\|bclri}}	Bit CLeaR Immediate	rd, rs, imm5/6	B
{{Mono\|bclr}}	Bit CLeaR	rd, rs1, rs2	B
{{Mono\|ori}}	OR Immediate	rd, rs, imm12	I
{{Mono\|or}}	OR	rd, rs1, rs2	I
{{Mono\|orn}}	OR Not	rd, rs1, rs2	B
{{Mono\|bseti}}	Bit SET Immediate	rd, rs, imm5/6	B
{{Mono\|bset}}	Bit SET	rd, rs1, rs2	B
{{Mono\|xori}}	eXclusive OR Immediate	rd, rs, imm12	I
{{Mono\|xor}}	eXclusive OR	rd, rs1, rs2	I
{{Mono\|xnor}}	Not XOR	rd, rs1, rs2	B
{{Mono \|binvi}}	Bit INVert Immediate	rd, rs, imm5/6	B
{{Mono \|binv}}	Bit INVert	rd, rs1, rs2	B
{{Mono\|not}}	NOT	rd, rs	I
{{Mono\|orc.b}}	OR Combine within Bytes	rd, rs	B
colspan="5" \|
{{Mono\|slli}}	Shift Left Logical Immediate	rd, rs, imm5/6	I
{{Mono\|sll}}	Shift Left Logical	rd, rs1, rs2	I
{{Mono\|slliw}}	Shift Left Logical Word Immediate	rd, rs, imm5	I	x
{{Mono\|sllw}}	Shift Left Logical Word	rd, rs1, rs2	I	x
{{Mono\|slli.wu}}	Shift Left Logical Word (U in double) Immediate	rd, rs, imm5/6	I	x
{{Mono\|srli}}	Shift Right Logical Immediate	rd, rs, imm5/6	I
{{Mono\|srl}}	Shift Right Logical	rd, rs1, rs2	I
{{Mono\|srliw}}	Shift Right Logical Word Immediate	rd, rs, imm5	I	x
{{Mono\|srlw}}	Shift Right Logical Word	rd, rs1, rs2	I	x
{{Mono\|srai}}	Shift Left Arith Immediate	rd, rs, imm5/6	I
{{Mono\|sra}}	Shift Right Arithmetic	rd, rs1, rs2	I
{{Mono\|sraiw}}	Shift Left Arith Word Immediate	rd, rs, imm5	I	x
{{Mono\|sraw}}	Shift Right Arithmetic Word	rd, rs1, rs2	I	x
{{Mono\|rori}}	ROtate Right Immediate	rd, rs, imm5/6	B
{{Mono\|ror}}	ROtate Right	rd, rs1, rs2	B
{{Mono\|rol}}	ROtate Left	rd, rs1, rs2	B
{{Mono\|roriw}}	ROtate Right Immediate Word	rd, rs, imm5	B	x
{{Mono\|rorw}}	ROtate Right Word	rd, rs1, rs2	B	x
{{Mono\|rolw}}	ROtate Left Word	rd, rs1, rs2	B	x
colspan="5" \|
{{Mono\|clz}}	Count Leading Zeros	rd, rs	B
{{Mono\|clzw}}	Count Leading Zeros in Word	rd, rs	B	x
{{Mono\|ctz}}	Count Trailing Zeros	rd, rs	B
{{Mono\|ctzw}}	Count Trailing Zeros in Word	rd, rs	B	x
{{Mono\|cpop}}	Count POPulation of 1s	rd, rs	B
{{Mono\|cpopw}}	Count POPulation of 1s in Word	rd, rs	B	x
colspan="5" \|
{{Mono\|j}}	Jump	label	I
{{Mono\|jal}}	Jump And Link	rd, imm20	I
{{Mono\|jr}}	Jump Register	rs [, imm12]	I
{{Mono\|jalr}}	Jump And Link Register	rd rs [, imm12]	I
{{Mono\|call}}	CALL	symbol	IAssembler macro clobbering ra. Interacts with the loader symbol relocation. Expands to jal ra, imm or auipc ra, imm; jalr ra, ra imm combination
{{Mono\|tail}}	TAIL call	symbol	IAssembler macro, may clobber t1. Interacts with the loader symbol relocation. Expands to jal zero imm or auipc t1, imm; jalr zero t1, imm combination
{{Mono\|ret}}	RETurn	-	IPseudo instruction clobbering ra. Expands to jal zero, ra, 0\|
colspan="5" \|
{{Mono\|beq}}	Branch ==	rs1, rs2, label	I
{{Mono\|bne}}	Branch !=	rs1, rs2, label	I
{{Mono\|blt}}	Branch <	rs1, rs2, label	I
{{Mono\|bgt}}	Branch >	rs1, rs2, label	I
{{Mono\|bge}}	Branch >=	rs1, rs2, label	I
{{Mono\|ble}}	Branch <=	rs1, rs2, label	I
{{Mono\|bltu}}	Branch < (U)	rs1, rs2, label	I
{{Mono\|bgtu}}	Branch > (U)	rs1, rs2, label	I
{{Mono\|bgeu}}	Branch >= (U)	rs1, rs2, label	I
{{Mono\|bleu}}	Branch <= (U)	rs1, rs2, label	I
colspan="5" \|
{{Mono\|nop}}	NoOPeration	-	I
{{Mono\|ecall}}	Environment CALL	-	I
{{Mono\|ebreak}}	Environment BREAK	-	I

Remarks

References

Category:Instruction set listings

Category:RISC-V

RISC-V instruction listings

RISC-V Integer Instructions

Remarks

See also

References