Root complex
{{Short description|A device connecting the CPU and memory to PCI Express switch fabric}}
[[File:Example PCI Express Topology.svg|thumb|right|upright=1.8|An example of the PCI Express topology, displaying the position of a root complex.{{cite web
| url = https://pcisig.com/sites/default/files/files/PCI_Express_Basics_Background.pdf#page=26
| title = PCI Express Basics and Background
| date = 2015-06-17 | accessdate = 2016-04-12
| author = Richard Solomon | publisher = PCI-SIG
| format = PDF | page = 26
}}]]
In a PCI Express (PCIe) system, a root complex device connects the CPU and memory subsystem to the PCI Express switch fabric composed of one or more PCIe or PCI devices. A root complex is sometimes referred to PCI root bridge.{{Cite web |title=14. Protocols — PCI Bus Support — UEFI Specification 2.10 documentation |url=https://uefi.org/specs/UEFI/2.10/14_Protocols_PCI_Bus_Support.html |access-date=2024-11-16 |website=uefi.org}}
The root complex generates transaction requests on behalf of the CPU, which is interconnected through a local bus. Root complex functionality may be integrated in the chipset and/or the CPU. A root complex may contain more than one PCI Express port and multiple switch devices can be connected to ports on the root complex or cascaded.{{cite web |url=http://www.rtcmagazine.com/articles/view/100327 |title=Choosing the Right Programmable Logic Solution for PCI Express Applications |accessdate=31 March 2010 |url-status=dead |archiveurl=https://web.archive.org/web/20110221044635/http://www.rtcmagazine.com/articles/view/100327 |archivedate=21 February 2011 }}{{Cite web|title=Bus Specifics (Writing Device Drivers)|url=https://docs.oracle.com/cd/E19683-01/806-5222/hwovr-22/|access-date=2020-11-14|website=docs.oracle.com}}
Device Memory Map
{{Refimprove|section|date=August 2012}}
The PCIe Root Complex holds a master copy of a 'Type 1 Configuration Table' that defines the host memory space that is accessible from each Endpoint device. In addition, each PCIe Endpoint device holds a master copy of their own memory space map in the host system memory as a 'Type 0 Configuration Table', this configuration table in each device allows the host to access the local memory of a PCIe device. Both the Type 1 and Type 0 configuration tables are set up by the Host Operating System that controls the Root Complex by a process known as enumeration and which acts to build a device memory map for the system by querying each bridge, and endpoint device connected on the bus network. Similarly, a PCIe Bridge acts a tiered root complex with a "Type 0 Configuration Table".