SIMM#72-pin SIMMs

{{Short description|Computer memory module}}

{{about|a type of memory module for computers}}

File:SIMM 30 68 72.png

A SIMM (single in-line memory module) is a type of memory module used in computers from the early 1980s to the early 2000s. It is a printed circuit board upon which multiple random-access memory Integrated circuit chips are attached to one or both sides.{{cite web | title=What is DIMM(Dual Inline Memory Module)? | website=GeeksforGeeks | date=2020-04-15 | url=https://www.geeksforgeeks.org/what-is-dimmdual-inline-memory-module/ | access-date=2024-04-07 | quote=In the case of SIMM, the connectors are only present on the single side of the module...DIMM has a row of connectors on both sides(front and back) of the module}} It differs from a dual in-line memory module (DIMM), the most predominant form of memory module since the late 1990s, in that the contacts on a SIMM are redundant on both sides of the module. SIMMs were standardised under the JEDEC JESD-21C standard.

Most early PC motherboards (8088-based PCs, XTs, and early ATs) used socketed DIP chips for DRAM. As computer memory capacities grew, memory modules were used to save motherboard space and ease memory expansion. Instead of plugging in eight or nine single DIP chips, only one additional memory module was needed to increase the memory of the computer.

History

SIMMs were invented in 1983 by James E. ClaytonClayton, James E. (1983). [https://books.google.com/books?id=mawpAQAAMAAJ&q=SIP Low-cost, high-density memory packaging: A 64K X 9 DRAM SIP module], The International journal for hybrid microelectronics. at Wang Laboratories with subsequent patents granted in 1987.{{US patent|4656605}} - Single in-line memory module

{{US patent|4727513}} - Signal in-line memory module Wang Laboratories litigated both patents against multiple companies.{{cite web |title=Wang Laboratories, Inc., Plaintiff/cross-appellant, v. Toshiba Corporation; Toshiba America Electronic Components, inc.; Toshiba America Information Systems, Inc., defendants-appellants, and Nec Corporation; Nec Electronics Inc. and Nec Technologies, inc., Defendants-appellants, and Molex Incorporated, Defendant, 993 F.2d 858 (Fed. Cir. 1993)|url=https://law.justia.com/cases/federal/appellate-courts/F2/993/858/310372/|website=justia.com|access-date=22 December 2023|date=May 10, 1993}}{{cite web |title=Wang Laboratories, Inc., Plaintiff-appellee, v. Clearpoint Research Corporation, Defendant-appellant, 5 F.3d 1504 (Fed. Cir. 1993)|url=https://law.justia.com/cases/federal/appellate-courts/F3/5/1504/626911/|website=justia.com|access-date=22 December 2023|date=July 23, 1993}}{{cite web |title=Wang Laboratories v. MITSUBISHI ELECTRONICS, 860 F. Supp. 1448 (C.D. Cal. 1993)|url=https://law.justia.com/cases/federal/district-courts/FSupp/860/1448/2159908/|website=justia.com|access-date=22 December 2023|date=December 17, 1993}}{{cite web |title=Wang Laboratories, Inc., Plaintiff-appellant, v. Mitsubishi Electronics America, Inc. and Mitsubishi Electric Corporation, Defendants/cross-appellants, 103 F.3d 1571 (Fed. Cir. 1997)|url=https://law.justia.com/cases/federal/appellate-courts/F3/103/1571/518294/|website=justia.com|access-date=22 December 2023|date=January 3, 1997}}{{cite web |title=Wang Laboratories v. OKI ELECTRIC INDUSTRY CO., 15 F. Supp. 2d 166 (D. Mass. 1998)|url=https://law.justia.com/cases/federal/district-courts/FSupp2/15/166/2314770/|website=justia.com|access-date=22 December 2023|date=July 31, 1998}} The original memory modules were built upon ceramic substrates with 64K Hitachi "flip chip" parts and had pins, i.e. single in-line package (SIP) packaging. SIMMs using pins are usually called SIP or SIPP memory modules to distinguish them from the more common modules using edge connectors.

The first variant of SIMMs has 30 pins and provides 8 bits of data (plus a 9th error-detection bit in parity SIMMs). They were used in AT-compatible (286-based, e.g., Wang APC[https://books.google.com/books?id=xsMx9D2s6y0C&pg=PA33 Wang Plays A Strong PC-Compatible Hand], PC Magazine, October 1, 1985), 386-based, 486-based, Macintosh Plus, Macintosh II, Quadra, Atari STE microcomputers, Wang VS minicomputers and Roland electronic samplers.

The second variant of SIMMs has 72 pins and provides 32 bits of data (36 bits in parity and ECC versions). These appeared first in the early 1990s in later models of the IBM PS/2, and later in systems based on the 486, Pentium, Pentium Pro, early Pentium II, and contemporary/competing chips of other brands. By the mid-90s, 72-pin SIMMs had replaced 30-pin SIMMs in new-build computers, and were starting to themselves be replaced by DIMMs.

Non-IBM PC computers such as UNIX workstations may use proprietary non-standard SIMMs. The Macintosh IIfx uses proprietary non-standard SIMMs with 64 pins.

DRAM technologies used in SIMMs include FPM (Fast Page Mode memory, used in all 30-pin and early 72-pin modules), and the higher-performance EDO DRAM (used in later 72-pin modules).

Due to the differing data bus widths of the memory modules and some processors, sometimes several modules must be installed in identical pairs or in identical groups of four to fill a memory bank. The rule of thumb is a 286, 386SX, 68000 or low-end 68020 / 68030 (e.g. Atari Falcon, Mac LC) system (using a 16 bit wide data bus) would require two 30-pin SIMMs for a memory bank. On 386DX, 486, and full-spec 68020 through 68060 (e.g. Atari TT, Amiga 4000, Mac II) systems (32 bit data bus), either four 30-pin SIMMs or one 72-pin SIMM are required for one memory bank. On Pentium systems (data bus width of 64 bits), two 72-pin SIMMs are required. However, some Pentium systems have support for a "half bank mode", in which the data bus would be shortened to only 32 bits to allow operation of a single SIMM. Conversely, some 386 and 486 systems use what is known as "memory interleaving", which requires twice as many SIMMs and effectively doubles the bandwidth.

The earliest SIMM sockets were conventional push-type sockets. These were soon replaced by ZIF sockets in which the SIMM was inserted at an angle, then tilted into an upright position. To remove one, the two metal or plastic clips at each end must be pulled to the side, then the SIMM must be tilted back and pulled out (low-profile sockets reversed this convention somewhat, like SODIMMs - the modules are inserted at a "high" angle, then pushed down to become more flush with the motherboard). The earlier sockets used plastic retainer clips which were found to break, so steel clips replaced them.

Some SIMMs support presence detect (PD). Connections are made to some of the pins that encode the capacity and speed of the SIMM, so that compatible equipment can detect the properties of the SIMM. PD SIMMs can be used in equipment which does not support PD; the information is ignored. Standard SIMMs can easily be converted to support PD by fitting jumpers, if the SIMMs have solder pads to do so, or by soldering wires on.[http://www.keycruncher.com/blog/2003/12/14/making-standard-simm-s-work-memory-upgrade-on-the-hp-laserjet-6mp-5mp/ Making Standard SIMMs Work – Memory Upgrade on the HP LaserJet 6MP/5MP Article on fitting jumpers to add Presence Detect to standard SIMMs]

30-pin SIMMs

File:Atari STE 256kB RAM 1.jpg

File:SIMM Bank.jpg motherboard]]

Standard sizes: 256 KB, 1 MB, 4 MB, 16 MB.

30-pin SIMMs have 12 address lines, which can provide a total of 24 address bits. With an 8-bit data width, this leads to an absolute maximum capacity of 16 MB for both parity and non-parity modules (the additional redundancy-bit chip usually does not contribute to the usable capacity).

class="wikitable"

|+ 30-pin SIMM

!Pin # !! Name !! Signal description

|rowspan=16|

!Pin # !! Name !! Signal description

1VCC+5 VDC

|16

DQ4Data 4
2/CASColumn address strobe

|17

A8Address 8
3DQ0Data 0

|18

A9Address 9
4A0Address 0

|19

A10Address 10
5A1Address 1

|20

DQ5Data 5
6DQ1Data 1

|21

/WEWrite enable
7A2Address 2

|22

VSSGround
8A3Address 3

|23

DQ6Data 6
9VSSGround

|24

A11Address 11
10DQ2Data 2

|25

DQ7Data 7
11A4Address 4

|26

QP*Data parity out
12A5Address 5

|27

/RASRow address strobe
13DQ3Data 3

|28

/CASP*Parity column address strobe
14A6Address 6

|29

DP*Data parity in
15A7Address 7

|30

VCC+5 VDC

* Pins 26, 28 and 29 are not connected on non-parity SIMMs.

72-pin SIMMs

Image:Edoram.jpg

Standard sizes: 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB (the standard also defines 3.3 V modules with additional address lines and up to 2 GB)

With 12 address lines, which can provide a total of 24 address bits, two ranks of chips, and 32-bit data output, the absolute maximum capacity is 227 = 128 MB.

class="wikitable"

|+5 V 72-pin SIMM

!Pin #!!Name!!Signal description

|rowspan=37|

!Pin #!!Name!!Signal description

1VSSGround

|37

MDP1*Data parity 1 (MD8..15)
2MD0Data 0

|38

MDP3*Data parity 3 (MD24..31)
3MD16Data 16

|39

VSSGround
4MD1Data 1

|40

/CAS0Column address strobe 0
5MD17Data 17

|41

/CAS2Column address strobe 2
6MD2Data 2

|42

/CAS3Column address strobe 3
7MD18Data 18

|43

/CAS1Column address strobe 1
8MD3Data 3

|44

/RAS0Row address strobe 0
9MD19Data 19

|45

/RAS1Row address strobe 1
10VCC+5 VDC

|46

NCNot connected
11NU [PD5#]Not used [presence detect 5 (3v3)]

|47

/WERead/write enable
12MA0Address 0

|48

NC [/ECC#]Not connected [ECC presence (if grounded) (3v3)]
13MA1Address 1

|49

MD8Data 8
14MA2Address 2

|50

MD24Data 24
15MA3Address 3

|51

MD9Data 9
16MA4Address 4

|52

MD25Data 25
17MA5Address 5

|53

MD10Data 10
18MA6Address 6

|54

MD26Data 26
19MA10Address 10

|55

MD11Data 11
20MD4Data 4

|56

MD27Data 27
21MD20Data 20

|57

MD12Data 12
22MD5Data 5

|58

MD28Data 28
23MD21Data 21

|59

VCC+5 VDC
24MD6Data 6

|60

MD29Data 29
25MD22Data 22

|61

MD13Data 13
26MD7Data 7

|62

MD30Data 30
27MD23Data 23

|63

MD14Data 14
28MA7Address 7

|64

MD31Data 31
29MA11Address 11

|65

MD15Data 15
30VCC+5 VDC

|66

NC [/EDO#]Not connected [EDO presence (if grounded) (3v3)]
31MA8Address 8

|67

PD1xPresence detect 1
32MA9Address 9

|68

PD2xPresence detect 2
33/RAS3Row address strobe 3

|69

PD3xPresence detect 3
34/RAS2Row Address Strobe 2

|70

PD4xPresence detect 4
35MDP2*Data parity 2 (MD16..23)

|71

NC [PD (ref)#]Not connected [presence detect (ref) (3v3)]
36MDP0*Data parity 0 (MD0..7)

|72

VSSGround

* Pins 35, 36, 37 and 38 are not connected on non-parity SIMMs.[http://www.jedec.org/sites/default/files/docs/4_04_02R8.PDF JEDEC Standard No. 21-C, Section 4.4.2] "72 pin SIMM DRAM Module Family".

/RAS1 and /RAS3 are only used on two-rank SIMMS: 2, 8, 32, and 128 MB.

# These lines are only defined on 3.3 V modules.

x Presence-detect signals are detailed in JEDEC standard.

Proprietary SIMMs

=GVP 64-pin=

Several CPU cards from Great Valley Products for the Commodore Amiga used special 64-pin SIMMs (32 bits wide, 1, 4 or 16 MB, 60 ns).

=Apple 64-pin=

Dual-ported 64-pin SIMMs were used in Apple Macintosh IIfx computers to allow overlapping read/write cycles (1, 4, 8, 16 MB, 80 ns).[http://www.lowendmac.com/ii/macintosh-iifx.html Macintosh IIfx].{{cite book | last = Apple Computer, Inc. | author-link = Apple Computer | title = Guide to the Macintosh Family Hardware | publisher = Addison-Wesley, Inc | year = 1990 | edition = 2nd | page = 230}}

class="wikitable"

|+ 5V 64-pin Mac IIfx SIMM{{cite book | last = Apple Computer, Inc. | author-link = Apple Computer | title = Guide to the Macintosh Family Hardware | publisher = Addison-Wesley, Inc | year = 1990 | edition = 2nd | pages = 214–222}}

!Pin #!!Name!!Signal description

|rowspan=33|

!Pin #!!Name!!Signal description

1GNDGround

|33

Q4Data output bus, bit 4
2NCNot connected

|34

/W4Write-enable input for RAM IC 4
3+5V+5 volts

|35

A8Address bus, bit 8
4+5V+5 volts

|36

NCNot connected
5/CASColumn address strobe

|37

A9Address bus, bit 9
6D0Data input bus, bit 0

|38

A10Address bus, bit 10
7Q0Data output bus, bit 0

|39

A11Address bus, bit 11
8/W0Write-enable input for RAM IC 0

|40

D5Data input bus, bit 5
9A0Address bus, bit 0

|41

Q5Data output bus, bit 5
10NCNot connected

|42

/W5Write-enable input for RAM IC 5
11A1Address bus, bit 1

|43

NCNot connected
12D1Data input bus, bit 1

|44

NCNot connected
13Q1Data output bus, bit 1

|45

GNDGround
14/W1Write-enable input for RAM IC 1

|46

D6Data input bus, bit 6
15A2Address bus, bit 2

|47

Q6Data output bus, bit 6
16NCNot connected

|48

/W6Write-enable input for RAM IC 6
17A3Address bus, bit 3

|49

NCNot connected
18GNDGround

|50

D7Data input bus, bit 7
19GNDGround

|51

Q7Data output bus, bit 7
20D2Data input bus, bit 2

|52

/W7Write-enable input for RAM IC 7
21Q2Data output bus, bit 2

|53

/QBReserved (parity)
22/W2Write-enable input for RAM IC 2

|54

NCNot connected
23A4Address bus, bit 4

|55

/RASRow address strobe
24NCNot connected

|56

NCNot connected
25A5Address bus, bit 5

|57

NCNot connected
26D3Data input bus, bit 3

|58

QParity-check output
27Q3Data output bus, bit 3

|59

/WWPWrite wrong parity
28/W3Write-enable input for RAM IC 3

|60

PDCIParity daisy-chain input
29A6Address bus, bit 6

|61

+5V+5 volts
30NCNot connected

|62

+5V+5 volts
31A7Address bus, bit 7

|63

PDCOParity daisy-chain output
32D4Data input bus, bit 4

|64

GNDGround

=HP LaserJet=

72-pin SIMMs with non-standard presence detect (PD) connections.

See also

References