Sam Naffziger
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| birth_name = Samuel Naffziger
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| alma_mater = California Institute of Technology (BS)
Stanford University (MSc)
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| employer = AMD
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Samuel Naffziger is an American electrical engineer who has been employed at Advanced Micro Devices in Fort Collins, Colorado since 2006. He was named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2014 for his leadership in the development of power management and low-power processor technologies.{{Cite web |title=2014 elevated fellow |url=https://www.ieee.org/2014Fellowclass |website=IEEE Fellows Directory |access-date=April 12, 2017 |archive-date=December 31, 2014 |archive-url=https://web.archive.org/web/20141231094853/http://www.ieee.org/2014Fellowclass |url-status=dead}} He is also the Senior Vice President and Product Technology Architect at AMD.{{cite web |title=Sam Naffziger |url=https://www.amd.com/en/corporate/leadership-sam-naffziger |website=AMD |language=en-US |access-date=April 3, 2023}}
Education
Naffziger received a Bachelor of Science degree in electrical engineering from the California Institute of Technology and a Master of Science in computer engineering from Stanford University.{{cite web |title=AMD Senior VP and Low-Power Guru, Samuel Naffziger, Addresses the Looming Electronics Power Challenge |url=https://www.allaboutcircuits.com/tech-days/summer-2022/amd/webinars/keynote-amds-sam-naffziger-senior-vice-president-corporate-fellow-and-product-technology-architect/ |website=All About Circuits |language=en-US |access-date=April 3, 2023}}
Career
= Early career =
For eight years, Naffziger led the Itanium design team at Hewlett-Packard before moving to Intel in 2002.{{cite web |last1=Kanellos |first1=Michael |date=January 25, 2002 |title=Intel’s Itanium: Plan B in the works |url=https://www.zdnet.com/article/intels-itanium-plan-b-in-the-works-5000120342/ |website=ZDNet |language=en-US |access-date=April 3, 2023}} At Intel, Naffziger played a leading role in the introduction of two major Itanium models at the International Solid State Circuits Conference, the McKinley processor in 2002 and Montecito in 2005.{{cite web |last1=Shankland |first1=Stephen |date=March 29, 2006 |title=AMD lures high-ranking Itanium designer |url=https://www.zdnet.com/article/amd-lures-high-ranking-itanium-designer/ |website=ZDNet |language=en-US |access-date=April 3, 2023}}
= 2006-present: Advanced Micro Devices =
Naffziger was an architect lead on AMD's Ryzen processors that launched in March 2017.{{cite web |last1=Chuang |first1=Tamara |date=March 3, 2017 |title=AMD unveils faster, half-price computer chip |url=https://www.denverpost.com/2017/03/03/amd-half-price-computer-chip/ |website=The Denver Post |language=en-US |access-date=April 3, 2023}} He was the lead advocate for AMD's Ryzen and Epyc lines to move to a modular, chiplet-based approach.{{Cite web |last1=Alcorn |first1=Paul |last2=Walton |first2=Jarred |date=June 23, 2022 |title=Into the GPU Chiplet Era: An Interview With AMD's Sam Naffziger |url=https://www.tomshardware.com/features/gpu-chiplet-era-interview-amd-sam-naffziger |website=Tom's Hardware |language=en-US |access-date=April 3, 2023}} Towards the end of 2017, Naffziger began to lead the AMD graphics team in bringing a chiplet architecture to graphics with the RDNA 3 architecture, released in 2022.{{Cite web |last1=Brosdahl |first1=Peter |date=November 22, 2022 |title=AMD Lead Engineer Sam Naffziger Explains Advantages of RDNA3 Chiplet Design |url=https://www.thefpsreview.com/2022/11/22/amd-lead-engineer-sam-naffziger-explains-advantages-of-rdna3-chiplet-design/ |website=The FPS Review |language=en-US |access-date=April 3, 2023}}
Academic works
- {{cite book |editor-last1=Wang |editor-first1=Alice |editor-last2=Naffziger |editor-first2=Samuel |year=2010 |title=Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice |url=https://download.e-bookshelf.de/download/0000/0023/81/L-G-0000002381-0002340532.pdf |location=Cham |publisher=Springer |isbn=978-0-387-76471-9}}
- {{cite journal |last1=Singh |first1=Teja |last2=Schaefer |first2=Alex |last3=Rangarajan |first3=Sundar |last4=John |first4=Deepesh |last5=Henrion |first5=Carson |last6=Schreiber |first6=Russell |last7=Rodriguez |first7=Miguel |last8=Kosonocky |first8=Stephen |last9=Naffziger |first9=Samuel |last10=Novak |first10=Amy |year=2018 |title=Zen: An Energy-Efficient High-Performance x86 Core |url=https://ieeexplore.ieee.org/document/8123510 |journal=IEEE Journal of Solid-State Circuits |volume=53 |issue=1 |pages=102-114}}
- {{cite conference |last1=Naffziger |first1=Samuel |last2=Beck |first2=Noah |last3=Burd |first3=Thomas |last4=Lepak |first4=Kevin |last5=Loh |first5=Gabriel H. |last6=Subramony |first6=Mahesh |last7=White |first7=Sean |year=2021 |title=Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families: Industrial Product |url=https://ieeexplore.ieee.org/document/9499852 |conference=2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA) |location=Valencia, Spain |pages=57-70}}
- {{cite conference |last1=Papermaster |first1=Mark |author1-link=Mark Papermaster |last2=Kosonocky |first2=Stephen |last3=Loh |first3=Gabriel H. |last4=Naffziger |first4=Samuel |year=2021 |title=A New Era of Tailored Computing |url=https://ieeexplore.ieee.org/document/9492400 |conference=2021 Symposium on VLSI Circuits |location=Kyoto, Japan |pages=1-2}}
- {{cite conference |last1=Wuu |first1=John |last2=Agarwal |first2=Rahul |last3=Ciraula |first3=Michael |last4=Dietz |first4=Carl |last5=Johnson |first5=Brett |last6=Johnson |first6=Dave |last7=Schreiber |first7=Russell |last8=Swaminathan |first8=Raja |last9=Walker |first9=Will |last10=Naffziger |first10=Samuel |year=2022 |title=3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU |url=https://ieeexplore.ieee.org/document/9731565 |conference=2022 IEEE International Solid- State Circuits Conference (ISSCC) |location=San Francisco, CA |pages=428-429}}
References
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Category:Year of birth missing (living people)
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Category:American electrical engineers
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