Scan chain

The conceptual origins of scan date back to the 1965, notably with IBM’s System/360 Model 50, which implemented scan-in and scan-out functions for processor self-diagnosis. Scan design, as formally applied to VLSI testing, gained traction after the landmark 1973 paper by Williams and Angell, and was widely advanced by IBM researchers including Eichelberger and Williams. {{Citation |title=Digital DFT and Scan Design |work=Frontiers in Electronic Testing |pages=465–488 |url=https://doi.org/10.1007/0-306-47040-3_14 |access-date=2025-06-08 |place=Boston |publisher=Kluwer Academic Publishers |isbn=0-7923-7991-8}}

In a full scan design, automatic test pattern generation (ATPG) is particularly simple. No sequential pattern generation is required - combinatorial tests, which are much easier to generate, will suffice. If you have a combinatorial test, it can be easily applied.

• Assert scan mode, and set up the desired inputs.
• De-assert scan mode, and apply one clock. Now the results of the test are captured in the target flip-flops.
• Re-assert scan mode, and see if the combinatorial test passed.

In a chip that does not have a full scan design -- i.e., the chip has sequential circuits, such as memory elements that are not part of the scan chain, sequential pattern generation is required. Test pattern generation for sequential circuits searches for a sequence of vectors to detect a particular fault through the space of all possible vector sequences.

Even a simple stuck-at fault requires a sequence of vectors for detection in a sequential circuit. Also, due to the presence of memory elements, the controllability and observability of the internal signals in a sequential circuit are in general much more difficult than those in a combinational logic circuit. These factors make the complexity of sequential ATPG much higher than that of combinational ATPG.

There are many variants:

• Partial scan: Only some of the flip-flops are connected into chains. This method reduces area and delay overhead, but requires more complex ATPG.
• Multiple scan chains: Two or more scan chains are built in parallel, to reduce the time to load and observe.
• Test compression: the input to the scan chain is provided by on-board logic.

Random-access scan (RAS) extends scan design by allowing individual flip-flops to be accessed like RAM cells via addressable selection. This enables rapid access and reduced scan time. However, the increased area from address decoders and control logic has limited its adoption.

Scan-Hold Flip-Flops (SHFFs) are a variant where a hold latch is added after the scan flip-flop. This design helps decouple scan and functional modes, making it ideal for delay fault testing. While SHFFs improve test control, they add both area (approx. 30%) and timing overhead.

Modern Electronic Design Automation (EDA) tools fully support scan insertion, rule checking, and ATPG vector generation. Scan design audits ensure compliance with DFT rules — such as using only D-type flip-flops, clock controllability, and separating scan and functional clocks. Once design verification is complete, automatic scan insertion tools can retrofit flip-flops, wire scan chains, and generate test vectors with high fault coverage.

Scan testing is especially critical in ASICs and SoCs, where internal nodes are otherwise unobservable. Despite area and timing costs, scan design remains the industry standard for testability and is supported by all major digital design flows.

• Design for testing
• Automatic test pattern generation
• Electronic design automation
• Integrated circuit design
• Serial Peripheral Interface Bus
• Iddq testing

• [https://web.archive.org/web/20150226004313/http://people.ee.duke.edu/~krish/teaching/ECE269/how_does_scan_work.pdf An example of a scan chain for stuck-at faults]
• [https://www.corelis.com/education/design-testability-tips-guidelines/boundary-scan-chain/ Boundary-Scan Chain]

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Category:Electronic circuit verification