Stanford DASH

Stanford DASH was a cache coherent multiprocessor developed in the late 1980s by a group led by Anoop Gupta, John L. Hennessy, Mark Horowitz, and Monica S. Lam at Stanford University.{{cite journal|title=The Stanford Dash Multiprocessor|last1=Lenoski|first1=Daniel|first2=James|last2=Laudon |first3=Kourosh|last3=Gharachorloo | first4=Wolf-Dietrich|last4=Weber |first5=Anoop|last5=Gupta |first6=John|last6=Hennessy |first7=Mark|last7=Horowitz |first8=Monica S.|last8=Lam|journal=Computer|volume=25|issue=3|year=1992|pages=63–79|doi=10.1109/2.121510|s2cid=9731523|url=http://dl.acm.org/citation.cfm?id=130562|url-access=subscription}} It was based on adding a pair of directory boards designed at Stanford to up to 16 SGI IRIS 4D Power Series machines and then cabling the systems in a mesh topology using a Stanford-modified version of the Torus Routing Chip.{{cite journal|title=The torus routing chip|last1=Dally|first1=William J.|first2=Charles L.|last2=Seitz |journal=Distributed Computing|volume=1|issue=4|year=1986|pages=187–196|doi=10.1007/BF01660031|s2cid=10500442}} The boards designed at Stanford implemented a directory-based cache coherence protocol{{cite conference|last1=Lenoski |first1=Daniel |last2=Laudon |first2=James|last3= Gharachorloo |first3=Kourosh|last4=Gupta |first4=Anoop|last5=Hennessy|first5=John |title=The directory-based cache coherence protocol for the DASH multiprocessor |book-title=Proceedings of the 17th Annual International symposium on Computer Architecture |publisher=ACM|pages=148–159 |date=1990|doi=10.1145/325164.325132}} allowing Stanford DASH to support distributed shared memory for up to 64 processors. Stanford DASH was also notable for both supporting and helping to formalize weak memory consistency models, including release consistency.{{cite conference|last1=Gharachorloo |first1=Kourosh |last2=Lenoski |first2=Daniel |last3=Laudon |first3=James|last4=Gibbons |first4=Phillip|last5=Gupta|first5=Anoop |last6=Hennessy|first6=John |title=Memory consistency and event ordering in scalable shared-memory multiprocessors |book-title=Proceedings of the 17th annual international symposium on Computer Architecture|pages=15–26 |date=1990|doi=10.1145/325096.325102}} Because Stanford DASH was the first operational machine to include scalable cache coherence,{{cite book|last1=Hennessy|first1=John|last2=Patterson|first2=David|title=Computer Architecture: A Quantitative Approach|url=https://archive.org/details/computerarchitec0003henn|url-access=registration|edition=Third|year=2003|pages=[https://archive.org/details/computerarchitec0003henn/page/655 655]|publisher=Morgan Kaufmann|isbn=978-1-558-60596-1}} it influenced subsequent computer science research as well as the commercially available SGI Origin 2000. Stanford DASH is included in the 25th anniversary retrospective of selected papers from the International Symposium on Computer Architecture{{cite conference|title=The DASH prototype: Implementation and Performance|book-title=25 years of the International Symposia on Computer Architecture (Selected Papers)|editor-last=Sohi|editor-first=Gurindar|last1=Lenoski|first1=Daniel|first2=James|last2=Laudon |first3=Truman|last3=Joe | first4=David|last4=Nakahira |first5=Luis|last5=Stevens |first7=John|last7=Hennessy |first6=Anoop|last6=Gupta|year=1998|pages=418–429|url=http://dl.acm.org/citation.cfm?id=285930}} and several computer science books,{{cite book|last1=Suzuki|first1=Norihisa|title=Shared Memory Multiprocessing|year=1992|pages=391–406|publisher=The MIT Press|isbn=978-0-262-19322-1}}{{cite book|last1=Loshin|first1=David|title=High Performance Computing Demystified|pages=[https://archive.org/details/highperformancec00losh/page/80 80, 91]|year=1994|publisher=Academic Press|isbn=978-0-124-55825-0|url-access=registration|url=https://archive.org/details/highperformancec00losh/page/80}}{{cite book|last1=Parhami|first1=Behrooz|title=Introduction to Parallel Processing: Algorithms and Architectures|pages=450–451|year=1999|publisher=Springer|isbn=978-0-306-45970-2}}{{cite book|last1 = Hill| first1 = Mark|author-link2=Norman Jouppi|last2=Jouppi|first2=Norman|last3=Sohi|first3=Gurindar| title = Readings in Computer Architecture|year=2000|pages=583–599|publisher=Morgan Kaufmann|isbn=978-1-55860-539-8|url=http://dl.acm.org/citation.cfm?id=333067}}{{cite book|last1= Dandamudi |first1= Sivarama|title=Hierarchical Scheduling in Parallel and Cluster Systems|url= https://archive.org/details/hierarchicalsche00dand |url-access= limited |year=2003|publisher=Springer US|pages=[https://archive.org/details/hierarchicalsche00dand/page/n40 21]–22|doi=10.1007/978-1-4615-0133-6|series= Series in Computer Science|isbn= 978-1-4613-4938-9|s2cid= 46434929}} has been simulated by the University of Edinburgh,Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh [http://www.icsa.informatics.ed.ac.uk/research/groups/hase/projects/dashclus/index.html "Stanford DASH Architecture: Cluster Simulation Model"], Retrieved on 3 November 2015. and is used as a case study in contemporary computer science classes.Carl Olson and Mattan Erez, The University of Texas at Austin (2007) [http://users.ece.utexas.edu/~merez/EE382V/lect17.pdf "The Stanford Dash Multiprocessor"], Retrieved on 3 November 2015.Meng Zhang, Duke University (2010) [http://people.ee.duke.edu/~sorin/ece259/presentations/dash-zhang.pdf "The Stanford Dash Multiprocessor"], Retrieved on 3 November 2015.