SuperSPARC

{{Infobox CPU

| name = SuperSPARC

| image = KL_TI_SuperSPARC.jpg

| image_size = 160px

| caption = The SuperSPARC microprocessor

| produced-start = 1992

| produced-end = 1995

| slowest = 33

| fastest = 90

| slow-unit = MHz

| fast-unit = MHz

| fsb-slowest =

| fsb-fastest =

| fsb-slow-unit =

| fsb-fast-unit =

| size-from =

| size-to =

| soldby =

| designfirm = Sun Microsystems

| manuf1 = Texas Instruments

| transistors = 3.1 million

| l2cache = none, 1 MB, 2 MB

| core1 =

| sock1 =

| pack1 =

| arch = SPARC V8

| microarch =

| numcores = 1

}}

The SuperSPARC is a microprocessor that implements the SPARC V8 instruction set architecture (ISA) developed by Sun Microsystems. 33 and 40 MHz versions were introduced in 1992. The SuperSPARC contains 3.1 million transistors. It was fabricated by Texas Instruments (TI) at Miho, Japan in a 0.8 micrometre triple-metal{{cite web |url=http://www.programd.com/48_a3f318541bdd7162_1.htm |title=SuperSPARC Microprocessor Fact Sheet |archive-url=https://web.archive.org/web/20150222225243/http://www.programd.com/48_a3f318541bdd7162_1.htm |archive-date=2015-02-22 |url-status=dead}} BiCMOS process.{{cite conference |url=https://www.researchgate.net/publication/3614178 |title=Testability features of the SuperSPARC microprocessor |book-title=Proceedings of IEEE International Test Conference - (ITC) |doi=10.1109/TEST.1993.470625 |date=1993}}

There are two derivatives of the SuperSPARC: the SuperSPARC+ and SuperSPARC-II. The SuperSPARC+ was developed to remedy some of the design flaws that limited the SuperSPARC's clock frequency and thus performance. The SuperSPARC-II, introduced in 1994, was a major revision with improvements that enabled the microprocessor to reach 85 MHz in desktop systems and 90 MHz in the more heavily cooled SPARCserver-1000E.

SuperSPARC CPU modules are used in both the SPARCstation 10 and SPARCstation 20.

The SuperSPARC-II was replaced in 1995 by the 64-bit UltraSPARC, an implementation of the 64-bit SPARC V9 ISA.