SystemC AMS

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A model of computation (MoC) is a set of rules defining the behavior and interaction between SystemC AMS primitive

modules. SystemC AMS defines the following models of computation: timed data flow (TDF), linear signal flow

(LSF) and electrical linear networks (ELN).

In the timed data flow (TDF) model, components exchange analogue values with each other

on a periodic basis at a chosen sampling rate, such as every 10 microseconds.

By the sampling theorem, this would be sufficient to convey

signals of up to 50 MHz bandwidth without aliasing artefacts.

A TDF model defines a method called `processing()' that is invoked

at the appropriate rate as simulation time advances.

A so-called cluster of models share a static schedule of when they should communicate.

This sets the relative ordering of the calls to the processing() methods

of each TDF instance in the cluster.

The periodic behaviour of TDF allows it to operate independently of the main

SystemC event-driven kernel used for digital logic.

The SystemC electrical linear networks (ELN) library provides a set of

standard electrical components that enable SPICE-like

simulations to be run. The three basic components, resistors, capacitors and

inductors are, of course, available. Further voltage-controlled variants, such as a transconductance

amplifier (voltage-controlled current generator) enable most FET and other

semiconductor models to be readily created.

Current flowing in ELN networks of resistors can be solved with a suitable simultaneous equation solver.

These are called the nodal equations.

Where time-varying components, such as capacitors and inductors are included, Euler's method is

typically implemented to model them.

Euler's method is a simple approach to solving finite-difference time-domain (FDTD) problems. For instance,

to simulate the capacitor charge problem on the left below, a timestep delta\_t is selected that is typically

about one percent of the time constant and the iteration on the bottom right is executed.

The error in Euler's method decreases quadratically with smaller time steps, but an overly-small time

step results in a slow simulation for a complex finite-element simulation. But this

is not a problem in many situations where part of a complex SoC or

plant controller is run alongside a plant model that has just a few state variables, such as the car transmission system because

there are orders of magnitude difference in time constants (e.g. 100 MHz clock versus 1~ms shortest inertial time constant).

Simulating the analogue subsystem inside the RTL simulator then makes sense.

Moreover, most plant control situations use closed-loop negative feedback with the controller being just as good at managing

a slightly errored plant model as the real model.

Under the ELN formalism, the SystemC initialisation and simulation cycles are extended to support solving nodal flow

equations. Nodal equation solving is generally solved iteratively

rather than using direct methods such as Gaussian Elimination or based

on matrix inverses. Iterative methods tend to have greater stability

and are fast when the state has only advanced slightly from the

previous time step. When the kernel de-queues a time-advancing event

from the event queue, the simulation time is advanced. The analogue

part of the simulator maintains a time quantum beyond which the nodal

equations need to be re-computed. This quantum is dynamically adjusted

depending on the behaviour of the equations. If the equations are

`bendy', meaning that linear extrapolation using Euler's method over

the quantum will lead to too much error, the time step is reduced,

otherwise it can be gradually enlarged at each step. Overall, two

forms of iteration are needed: the first is iteration at a time step to solve

the nodal equations to a sufficient accuracy. The second is between

time steps. In a simple implementation, once simulation time has

advanced beyond the Euler quantum, the analogue sub-system is

re-solved. If the extrapolation errors are too great, the simulator

must go back to the last time step and simulate forward again using a

smaller analogue quantum. This mechanism is also the basis for SPICE

simulations.

Each analogue variable that is the argument to a `cross',

or other analogue sensitivity, is then examined to see if new digital

domain work has been triggered. If so, new events are injected on the discrete event

queue for the current simulation time.

The SystemC linear signal flow (LSF) library provides a set of primitive

analogue operators, such as adders and differentiators that enable

all basic structures found in differential equations to be

constructed in a self-documenting and executable form. The

advantage of constructing the system from a standard operator library

is that `reflection' is possible: other code can analyse the structure

and perform analytic differentiation, summation, integration

and other forms of analysis, such as sensitivity analysis to determine

a good time step.

This would not be possible for an implementation using ad-hoc coding.

In general programming, reflection refers to

a program being able to read its own source code.

TDF in/outport definition:

sca_tdf::sca_in

sca_tdf::sca_out

TDF converter in/outport definition:

sca_tdf::sc_in // DE → TDF inport

sca_tdf::sc_out // TDF → DE outport

ELN terminal definition:

sca_eln::sca_terminal

sca_eln::sca_node // ELN node

sca_eln::sca_node_ref // ELN reference node

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sca_trace_file *tf = sca_create_tabular_trace_file("trace_file_name.dat");

sca_trace(tf, , "name");

Timed-Data-Flow 1st order low pass model:

1. include

using namespace sca_util; // introduced for convenience: sca_util::sca_vector → sca_vector

using namespace sca_core; // introduced for convenience: sca_core::sca_time() → sca_time()

using namespace sca_ac_analysis; // introduced for convenience: sca_ac_analysis::sca_ac() → sca_ac()

SCA_TDF_MODULE(tdf_low_pass)

{

// TDF ports

sca_tdf::sca_in inp;

sca_tdf::sca_out outp;

// parameters

double fcut; // cut-off frequency

// methods

void initialize(); // simulator callback for initialization purpose

void ac_processing(); // simulator callback for AC behavior implementation

void processing(); // simulator callback for time implementation

// constructor

SCA_CTOR(tdf_low_pass) {

fcut = 1.0e3; // cut-off frequency 1kHz

}

private:

sca_vector num; // numerator coefficients

sca_vector den; // de-numerator coefficients

sca_vector state; // state vector

sca_tdf::sca_ltf_nd ltf_nd; // linear transfer function (numerator/de-numerator type)

};

linear transfer function:

$H(s)\; =\; \backslash frac\{1\}\{1+\backslash frac\{1\}\{2*\backslash pi*f\_\backslash mathrm\{cut\}\}s\}$

// initialize linear transfer function coefficients

void tdf_low_pass::initialize(){

num(0) = 1.0;

den(0) = 1.0;

den(1) = 1.0/(2.0*M_PI*fcut);

}

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// AC implementation

void tdf_low_pass::ac_processing(){

sca_ac(outp) = sca_ac_ltf_nd(num, den, sca_ac(inp));

}

ToDo: description

// time domain implementation

void tdf_low_pass::processing(){

outp = ltf_nd(num, den, state, inp);

}

Electrical-Linear-Networks 1st order low pass netlist:

SC_MODULE(eln_low_pass_netlist)

{

// sca eln terminals

sca_eln::sca_terminal n1;

sca_eln::sca_terminal n2;

// internal nodes

sca_eln::sca_node_ref gnd;

// eln modules

sca_eln::sca_r i_r;

sca_eln::sca_c i_c;

SC_CTOR(eln_low_pass_netlist) : i_r("i_r"), i_c("i_c")

{

i_r.value = 1.0;

i_r.p.bind(n1);

i_r.n.bind(n2);

i_c.value = 1.0/(2.0*M_PI*1.0e3);

i_c.p.bind(n2);

i_c.n.bind(gnd);

}

};

Linear-Signal-Flow netlist:

SystemC AMS study group was founded in 2002 to develop and maintain analog and mixed-signal extensions to SystemC, and to initiate an OSCI (Open SystemC initiative) SystemC-AMS working group. The study group has made initial investigations and specified and implemented a SystemC extension to demonstrate feasibility of the approach. In 2006, a SystemC AMS working group has been funded which continued the work of the study group inside OSCI, and now goes on to work on SystemC AMS within the Accellera Systems Initiative, resulting in the AMS 1.0 standard in 2010. After the release of the Accellera SystemC AMS 2.0 standard in 2013, the standard was transferred to the IEEE Standards Association in 2014 for further industry adoption and maintenance. The SystemC AMS standard was released April 6, 2016 as IEEE Std 1666.1-2016.{{Cite web|url=http://accellera.org/activities/working-groups/systemc-ams|title=SystemC AMS (Analog/Mixed-Signal)|website=accellera.org|access-date=2016-08-01}}{{Cite web|url=http://www.systemc-ams.org/|title=SystemC-AMS and Design of Embedded Mixed-Signal Systems|website=www.systemc-ams.org|access-date=2016-08-01}} COSEDA Technologies provides with COSIDE the first commercially available design environment based on SystemC AMS standard.

• [https://web.archive.org/web/20160414120940/http://standards.ieee.org/getieee/1666_1/download/1666_1-2016.pdf SystemC AMS-Standard IEEE 1666.1-2016]
• [http://www.coseda-tech.com/systemc-ams-proof-of-concept SystemC AMS Proof-of-Concept Download]

{{Reflist}}

• [https://americodias.com/docs/systemc-ams/pll.md Phase Locked Loop simulator in SystemC AMS] - Américo Dias - Keywords: Phase Locked Loop, PLL, SystemC-AMS
• [http://systemc-ams.at/ SystemC AMS examples] - Wolfgang Scherr - Keywords: Filter, ADC, SystemC-AMS

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