SystemRDL
{{Short description|Language to describe control status registers}}
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The SystemRDL language, supported by the SPIRIT Consortium, was specifically designed to describe and implement a wide variety of control status registers. Using SystemRDL, developers can automatically generate and synchronize register views for specification, hardware design, software development, verification, and documentation.
SystemRDL is an open source text based descriptive language that focuses exclusively on registers. SystemRDL 1.0 had some limitations and is now superseded by SystemRDL 2.0 which has support for verification based properties like constraints, coverage, and HDL paths. SystemRDL 2.0 also introduces the ability to parameterize components which further improves design re-use.
See also
Companies/tools
- Commercial
- Agnisys [https://www.agnisys.com/products/idesignspec-uvm-register-generator/ Agnisys IDesignSpec]
- Semifore's CSR Compiler[http://semifore.com/csrcompiler/ Semifore's CSR Compiler]
- Magillem [http://blog.magillem.com/system-rdl Magillem system-rdl]
- Open Source
- Open Register Design Tool released by Juniper Networks under Apache 2.0 open source license[https://github.com/Juniper/open-register-design-tool Open Register Design Tool]
- SystemRDL compiler at GitHub supports SystemRDL 2.0 and generators for documentation and IP-XACT.[https://github.com/SystemRDL github.com SystemRDL compiler]
References
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External links
- [https://www.accellera.org/downloads/standards/systemrdl SystemRDL] Accellera Standards
- [https://www.denali.com/en/partners/rdl.jsp SystemRDL Alliance]
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Category:Hardware description languages
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