TILE64

{{Use mdy dates|date=November 2015}}

{{Infobox CPU

| name = TILE64

| image =

| image_size =

| caption =

| produced-start = 2007

| produced-end =

| slowest = 600

| fastest = 900

| slow-unit = MHz

| fast-unit = MHz

| fsb-slowest =

| fsb-fastest =

| fsb-slow-unit =

| fsb-fast-unit =

| size-from = 45 nm

| size-to = 90 nm

| manuf1 = Tilera

| core1 =

| sock1 =

| arch =

| microarch =

| numcores = 64

}}

TILE64{{cite book |url=https://books.google.com/books?id=aLaRfJq-59sC&q=Tilera+TILE+isa+vliw&pg=PA29 |title=Multicore Processors and Systems - Google Books |format= |isbn=9781441902634 |accessdate=|last1=Keckler |first1=Stephen W. |last2=Olukotun |first2=Kunle |last3=Peter Hofstee |first3=H. |date=August 29, 2009 |publisher=Springer }} is a VLIW ISA multicore processor manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor.

The short-pipeline, in-order, three-issue cores implement a MIPS-inspired{{Cite web|url=https://stackoverflow.com/questions/6515358/what-instruction-set-is-used-by-tilera-microprocessors|title = Compiler construction - What instruction set is used by Tilera microprocessors?}} VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load–store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches.{{cite news |title=Massively multicore processor runs Linux |url=http://www.linuxdevices.com/news/NS8981295285.html |publisher=linuxdevices.com |first=Henry |last=Kingman |date=August 20, 2007 |archiveurl=https://archive.today/20120906054352/http://www.linuxfordevices.com/c/a/News/Massively-multicore-processor-runs-Linux/ |archivedate=September 6, 2012 |url-status=dead |df=mdy-all }} A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system.

TILE64 has four DDR2 controllers, two 10-gigabit Ethernet interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 900 MHz.

Image:Tile64.svg | Image:Tile64-Tile.svg

According to CTO and co-founder Anant Agarwal, Tilera will target the chip at networking equipment and digital video markets where the demands for computing processing are high.{{cite news |first=Mark |last=Boslet |title=Start-up Tilera to Unveil 64-core chip |url=http://origin.mercurynews.com/businessheadlines/ci_6668379 |archive-url=https://web.archive.org/web/20071112085140/http://origin.mercurynews.com/businessheadlines/ci_6668379 |url-status=dead |archive-date=November 12, 2007 |work=San Jose Mercury News |date=August 20, 2007 }}

Support for the TILE64 architecture was added to Linux kernel version 2.6.36{{cite web |title=Tilera architecture support |url=http://kernelnewbies.org/Linux_2_6_36#head-3f060090317e345261a208f3ed5a3d639a71bbcb |publisher=Kernel Newbies |date=October 20, 2010 }} but was dropped in kernel version 4.16.{{cite news|author1=Simon Sharwood|title=Linux 4.16 arrives, erases eight CPUs and keeps melting Meltdown|url=https://www.theregister.co.uk/2018/04/03/linux_4_16_released/|accessdate=3 April 2018|work=theregister.co.uk|publisher=Situation Publishing|date=3 April 2018|archiveurl=https://web.archive.org/web/20180403102729/https://www.theregister.co.uk/2018/04/03/linux_4_16_released/|archivedate=3 April 2018}} A non-official LLVM back-end for Tilera exists.[https://www.phoronix.com/scan.php?page=news_item&px=MTE3NzE Tilera TILE64 Back-End For LLVM Published] // Phoronix, September 6, 2012