Tile processor
{{multiple issues|
{{COI|date=October 2010}}
{{Update|date=April 2017}}
{{Update|inaccurate=yes|date=April 2017}}
}}
Tile processors{{cite journal |url=https://ieeexplore.ieee.org/document/7482495 |title=The Tile Processor™ architecture: Embedded multicore for networking and digital multimedia - IEEE Conference Publication |format= |journal= |date=August 2007 |pages=1–12 |doi=10.1109/HOTCHIPS.2007.7482495 |s2cid=44858928 |accessdate=|url-access=subscription }} for computer hardware, are multi-core or manycore chips that contain one-dimensional, or more commonly, two-dimensional arrays of identical tiles. Each tile comprises a compute unit (or a processing engine or CPU), caches and a switch. Tiles can be viewed as adding a switch to each core, where a core comprises a compute unit and caches.
In a typical Tile Processor configuration, the switches in each of the tiles are connected to each other using one or more mesh networks.{{cite news |title=On-Chip Interconnection Architecture of the Tile Processor |url=http://www.princeton.edu/~wentzlaf/documents/Wentzlaff.2007.IEEE_Micro.Tilera.pdf |publisher=IEEE Micro |first=David |last=Wentzlaff |date=September 15, 2007 }} doi:10.1109/MM.2007.89 The Tilera TILEPro64, for example, contains 64 tiles. Each of the tiles comprises a CPU, L1 and L2 caches, and switches for several mesh networks.
Other processors in a tile configuration include SEAforth24, Kilocore KC256, XMOS xCORE microcontrollers, and some massively parallel processor arrays.