VAX

{{Short description|Line of computers sold by Digital Equipment Corporation}}

{{Infobox CPU architecture

| name = VAX

| image = VAX logo.svg

| designer = Digital Equipment Corporation

| bits = 32-bit

| introduced = {{Start date and age|1977}}

| design = CISC

| type = {{ubl | Register–register | Register–memory | Memory–memory }}

| encoding = Variable (1 to 56 bytes)

| endianness = Little

| extensions = PDP-11 compatibility mode, VAX Vector Extensions,{{cite web |url=http://www.openvms.compaq.com/doc/73final/4515/4515pro_012.html#basic_arch_sect |title=VAX MACRO and Instruction Set Reference Manual |at=8.1 Basic Architecture |date=April 2001 |work=OpenVMS documentation |archive-url=https://web.archive.org/web/20010906051514/http://www.openvms.compaq.com/doc/73final/4515/4515pro_012.html#basic_arch_sect |archive-date=September 6, 2001 |url-status=dead}} VAX Virtualization Extensions{{cite book|url=http://www.bitsavers.org/pdf/dec/vax/archSpec/EL-00032-00-decStd32_Jan90.pdf|title=DEC STD 032 – VAX Architecture Standard|date=January 5, 1990|publisher=Digital Equipment Corp|page=12-5|access-date=2022-08-01}}

| open = No

| branching = Condition code

| page size = 512 bytes

| predecessor = PDP-11

| successor = Alpha

| gpr = 16 × 32-bit

| fpr = not present, uses the GPR

| vpr = 16 × 4096-bit (64 elements of 64 bits each)

}}

VAX (an acronym for virtual address extension) is a series of computers featuring a 32-bit instruction set architecture (ISA) and virtual memory that was developed and sold by Digital Equipment Corporation (DEC) in the late 20th century. The VAX-11/780, introduced October 25, 1977, was the first of a range of popular and influential computers implementing the VAX ISA. The VAX family was a huge success for DEC, with the last members arriving in the early 1990s. The VAX was succeeded by the DEC Alpha, which included several features from VAX machines to make porting from the VAX easier.

VAX was designed as a successor to the 16-bit PDP-11, one of the most successful minicomputers in history with approximately 600,000 units sold. The system was designed to offer backward compatibility with the PDP-11 while extending the memory to a full 32-bit implementation and adding demand paged virtual memory. The name VAX refers to its virtual address extension concept that allowed programs to make use of this newly available memory while still being compatible with unmodified user mode PDP-11 code. The name "VAX-11", used on early models, was chosen to highlight this capability. The VAX ISA is considered a complex instruction set computer (CISC) design.

DEC quickly dropped the −11 branding as PDP-11 compatibility was no longer a major concern. The line expanded to both high-end mainframes like the VAX 9000 as well as to the workstation-scale systems like the VAXstation series. The VAX family ultimately contained ten distinct designs and over 100 individual models in total. All of them were compatible with each other and normally ran the VAX/VMS operating system.

VAX has been perceived as the quintessential CISC ISA,{{cite web |last1=Bistriceanu |first1=Virgil |title=Computer Architecture – Class notes |url=http://www.cs.iit.edu/~virgil/cs470/Book/chapter3.pdf |publisher=Illinois Institute of Technology |access-date=April 15, 2022}} with its very large number of assembly language programmer-friendly addressing modes and machine instructions, highly orthogonal instruction set architecture, and instructions for complex operations such as queue insertion or deletion, number formatting, and polynomial evaluation.{{cite journal |last1=Payne |first1=Mary |last2=Bhandarkar |first2=Dileep |year=1980 |title=VAX floating point: a solid foundation for numerical computation |journal=ACM SIGARCH Computer Architecture News |publisher=ACM |volume=8 |issue=4 |pages=22–33 |issn=0163-5964 |doi=10.1145/641845.641849 |s2cid=15021135|doi-access=free }}

Name

File:VAX 11-780 intero.jpg

The name "VAX" originated as an acronym for virtual address extension, both because the VAX was seen as a 32-bit extension of the older 16-bit PDP-11 and because it was (after Prime Computer) an early adopter of virtual memory to manage this larger address space.

Early versions of the VAX processor implement a "compatibility mode" that emulates many of the PDP-11's instructions, giving it the 11 in VAX-11 to highlight this compatibility. Later versions offloaded the compatibility mode and some of the less used CISC instructions to emulation in the operating system software.

Instruction set

The VAX instruction set was designed to be powerful and orthogonal.{{Cite book|url=https://books.google.com/books?id=3LijBQAAQBAJ|title=Computer Programming and Architecture: The Vax|last1=Levy|first1=Henry|last2=Eckhouse|first2=Richard|date=June 28, 2014|publisher=Digital Press|isbn=9781483299372|language=en}} When it was introduced, many programs were written in assembly language, so having a "programmer-friendly" instruction set was important.{{cite web

|title=Another Approach to Instruction Set Architecture—VAX

|url=http://www.weblearn.hs-bremen.de/risse/RST/docs/COD2e/WebExtns.ion/webext3.pdf

|quote=... instruction set architectures, we chose the VAX as programmer-friendly instruction set, an asset

|access-date=October 3, 2018

|archive-date=June 10, 2017

|archive-url=https://web.archive.org/web/20170610060129/http://www.weblearn.hs-bremen.de/risse/RST/docs/COD2e/WebExtns.ion/webext3.pdf

|url-status=dead

}}{{cite web |title=VAX |quote=Esp. noted for its large, assembler-programmer-friendly instruction set --- an asset that|url=http://www.lysator.liu.se/hackdict/split/vax.html}} In time, as more programs were written in high-level programming languages, the instruction set became less visible, and the only ones much concerned about it were compiler writers.

One unusual aspect of the VAX instruction set is the presence of register masks{{cite web |url=http://www.openvms.compaq.com/doc/73final/4515/4515pro_020.html#index_x_790 |title=VAX MACRO and Instruction Set Reference Manual |at=9.2.5 Procedure Call Instructions |date=April 2001 |work=OpenVMS documentation |archive-url=https://web.archive.org/web/20020330111145/http://www.openvms.compaq.com/doc/73final/4515/4515pro_020.html#index_x_790 |archive-date=March 30, 2002 |url-status=dead}} at the start of each subprogram. These are arbitrary bit patterns that specify, when control is passed to the subprogram, which registers are to be preserved. On most architectures, it is up to the compiler to produce instructions to save out the needed data, typically using the call stack for temporary storage. On the VAX, with 16 registers, this might require 16 instructions to save the data and another 16 to restore it. Using the mask, a single 16-bit value performs the same operations internally in hardware, saving time and memory.

Since register masks are a form of data embedded within the executable code, they can make linear parsing of the machine code difficult. This can complicate optimization techniques that are applied on machine code.{{cite thesis |last=Goss |first=Clinton F. |date=August 2013 |title=Machine Code Optimization: Improving Executable Object Code |type=PhD |orig-date=First published June 1986 |volume=Computer Science Department Technical Report No. 246 |publisher=Courant Institute, New York University |url=http://www.ClintGoss.com/mco/Goss_1986_MachineCodeOptimization.pdf |access-date=August 22, 2013 |arxiv=1308.4815 |bibcode=2013arXiv1308.4815G}}

{{cite thesis |degree=PhD |author=Clinton F. Goss |date=2013 |orig-date=1986 |title=Machine Code Optimization – Improving Executable Object Code | publisher=Courant Institute, New York University |url=http://www.ClintGoss.com/mco/}}

Operating systems

File:VAX VMS logo.svg

The native VAX operating system is Digital's VAX/VMS (renamed to OpenVMS in 1991 or early 1992 when it was ported to Alpha, modified to comply with POSIX standards, and branded as compliant with XPG4 by the X/Open consortium).{{Cite web |editor1-last=Rainville |editor1-first=Jim |editor2-last=Howard |editor2-first=Karen |year=1997 |url=http://h41379.www4.hpe.com/openvms/20th/ |title=VAX/VMS at 20 |publisher=Digital Equipment Corporation |access-date=July 20, 2018 |archive-url=https://web.archive.org/web/20180720225439/http://h41379.www4.hpe.com/openvms/20th/ |archive-date=July 20, 2018 |url-status=dead}} The VAX architecture and VMS operating system were "engineered concurrently" to take maximum advantage of each other, as was the initial implementation of the VAXcluster facility.

During the 1980s, a hypervisor for the VAX architecture named VMM (Virtual Machine Monitor), also known as the VAX Security Kernel, was developed at Digital with the aim of allowing multiple isolated instances of VMS and ULTRIX to be run on the same hardware.{{cite conference|url=https://www.scs.stanford.edu/nyu/04fa/sched/readings/vmm.pdf|title=A VMM security kernel for the VAX architecture|author1=Paul A. Karger|author2=Mary Ellen Zurko|author3=Douglas W. Benin|author4=Andrew H. Mason|author5=Clifford E. Kahnh|date=May 7–9, 1990|conference=Proceedings. 1990 IEEE Computer Society Symposium on Research in Security and Privacy|access-date=2021-01-31|publisher=IEEE|doi=10.1109/RISP.1990.63834}} VMM was intended to achieve TCSEC A1 compliance. By the late 1980s, it was operational on VAX 8000 series hardware, but was abandoned before release to customers.

Other VAX operating systems have included various releases of Berkeley Software Distribution (BSD) UNIX up to 4.3BSD, Ultrix-32, VAXELN, and Xinu. More recently, NetBSD{{cite web|url=http://wiki.netbsd.org/ports/vax/|title=NetBSD/vax}} and OpenBSD{{cite web|url=http://www.openbsd.org/vax.html|title=OpenBSD/vax}} have supported various VAX models and some work has been done on porting Linux to the VAX architecture.{{cite web|url=http://vax-linux.org|title=Porting Linux to the VAX}} OpenBSD discontinued support for the architecture in September 2016.{{Cite web |url=https://www.openbsd.org/60.html |title=OpenBSD 6.0 |year=2016 |access-date=June 20, 2017}}

History

File:DEC-VAX-8350-front-0a.jpg

The first VAX model sold was the VAX-11/780, which was introduced on October 25, 1977, at the Digital Equipment Corporation's Annual Meeting of Shareholders.{{cite web |url=https://www.old-computers.com/history/detail.asp?n=20&t=3 |title=VAX 11/780, The First VAX System (October 1977)}} Bill Strecker, C. Gordon Bell's doctoral student at Carnegie Mellon University, was responsible for the architecture.{{Cite book |url=https://books.google.com/books?id=aWTtMyYmKhUC&q=%22Bill+Strecker%22+vax+designer |title=Portraits in Silicon |last=Slater |first=Robert |publisher=MIT Press |year=1987 |page=[https://books.google.com/books?id=aWTtMyYmKhUC&pg=PA213&lpg=PA213&dq=%22Bill+Strecker%22+vax+designer 213] |isbn=978-0-262-69131-4}} Many different models with different prices, performance levels, and capacities were subsequently created. VAX superminicomputers were very popular in the early 1980s.

For a while the VAX-11/780 was used as a standard in CPU benchmarks. It was initially described as a one-MIPS machine, because its performance was equivalent to an IBM System/360 that ran at one MIPS, and the System/360 implementations had previously been de facto performance standards. The actual number of instructions executed in 1 second was about 500,000, which led to complaints of marketing exaggeration. The result was the definition of a "VAX MIPS", the speed of a VAX-11/780; a computer performing at 27 VAX MIPS would run the same program roughly 27 times faster than the VAX-11/780.

Within the Digital community the term VUP (VAX Unit of Performance) was the more common term, because MIPS do not compare well across different architectures. The related term cluster VUPs was informally used to describe the aggregate performance of a VAXcluster. (The performance of the VAX-11/780 still serves as the baseline metric in the BRL-CAD Benchmark, a performance analysis suite included in the BRL-CAD solid modeling software distribution.) The VAX-11/780 included a subordinate stand-alone LSI-11 computer that performed microcode load, booting, and diagnostic functions for the parent computer. This was dropped from subsequent VAX models. Enterprising VAX-11/780 users could therefore run three different Digital Equipment Corporation operating systems: VMS on the VAX processor (from the hard drives), and either RSX-11S or RT-11 on the LSI-11 (from the single density single drive floppy disk).

The VAX went through many different implementations. The original VAX 11/780 was implemented in TTL and filled a four-by-five-foot cabinet{{cite web |title=VAX 11/780 Computer: CPU |url=http://www.computerhistory.org/revolution/mainframe-computers/7/182/736 |publisher=Computer History Museum |access-date=October 24, 2012}} with a single CPU. Through the 1980s, the high-end of the family was continually improved using ever-faster discrete components, an evolution that ended with the introduction of the VAX 9000 in October 1989. This design proved too complex and expensive and was ultimately abandoned not long after introduction. CPU implementations that consisted of multiple emitter-coupled logic (ECL) gate array or macrocell array chips included the VAX 8600 and 8800 superminis and finally the VAX 9000 mainframe class machines. CPU implementations that consisted of multiple MOSFET custom chips included the 8100 and 8200 class machines. The VAX 11-730 and 725 low-end machines were built using AMD Am2901 bit-slice components for the ALU.

The MicroVAX I represented a major transition within the VAX family. At the time of its design, it was not yet possible to implement the full VAX architecture as a single VLSI chip (or even a few VLSI chips as was later done with the V-11 CPU of the VAX 8200/8300). Instead, the MicroVAX I was the first VAX implementation to move some of the more complex VAX instructions (such as the packed decimal and related opcodes) into emulation software. This partitioning substantially reduced the amount of microcode required and was referred to as the "MicroVAX" architecture. In the MicroVAX I, the ALU and registers were implemented as a single gate-array chip while the rest of the machine control was conventional logic.

A full VLSI (microprocessor) implementation of the MicroVAX architecture arrived with the MicroVAX II's 78032 (or DC333) CPU and 78132 (DC335) FPU. The 78032 was the first microprocessor with an on-board memory management unit{{cite web|url=http://simh.trailing-edge.com/semi/uvax.html|website=Computer History and Simulation|title=MicroVAX II (1985)}} The MicroVAX II was based on a single, quad-sized processor board which carried the processor chips and ran the MicroVMS or Ultrix-32 operating systems. The machine featured 1 MB of on-board memory and a Q22-bus interface with DMA transfers. The MicroVAX II was succeeded by many further MicroVAX models with much improved performance and memory.

Further VLSI VAX processors followed in the form of the V-11, CVAX, CVAX SOC ("System On Chip", a single-chip CVAX), Rigel, Mariah and NVAX implementations. The VAX microprocessors extended the architecture to inexpensive workstations and later also supplanted the high-end VAX models. This wide range of platforms (mainframe to workstation) using one architecture was unique in the computer industry at that time. Sundry graphics were etched onto the CVAX microprocessor die. The phrase CVAX... when you care enough to steal the very best was etched in broken Russian as a play on a Hallmark Cards slogan, intended as a message to Soviet engineers who were known to be both purloining DEC computers for military applications and reverse engineering their chip design.{{cite web|website=micro.magnet.fsu.edu|url=http://micro.magnet.fsu.edu/creatures/pages/russians.html|title=Steal the best|access-date=January 30, 2008}} The Russian phrase was: {{lang|ru|СВАКС... Когда вы забатите довольно воровать настоящий лучший}}{{cite web|url=http://simh.trailing-edge.com/semi/cvax.html|website=Computer History and Simulation|title=CVAX (1987)|access-date=January 30, 2008}} By the late 1980s, the VAX microprocessors had grown in power to be competitive with discrete designs. This led to the abandonment of the 8000 and 9000 series and their replacement by Rigel-powered models of the VAX 6000, and later by NVAX-powered VAX 7000 systems.

In DEC's product offerings, the VAX architecture was eventually superseded by RISC technology. In 1989 DEC introduced a range of workstations and servers that ran Ultrix, the DECstation and DECsystem respectively, using processors from MIPS Computer Systems. In 1992 DEC introduced their own RISC instruction set architecture, the Alpha AXP (later renamed Alpha), and their own Alpha-based microprocessor, the DECchip 21064, a high performance 64-bit design capable of running OpenVMS.

In August 2000, Compaq announced that the remaining VAX models would be discontinued by the end of the year,{{cite web|url=http://www.compaq.com/alphaserver/vax/vax_letter_final.html |title=VAX Systems: A letter from Jesse Lipcon |archive-url=https://web.archive.org/web/20000815201016/http://www.compaq.com/alphaserver/vax/vax_letter_final.html |archive-date=August 15, 2000 |url-status=dead}} but old systems remain in widespread use.{{Cite web|url=https://www.pcworld.com/article/468250/if-it-aint-broke-dont-fix-it-ancient-computers-in-use-today.html|title=If It Ain't Broke, Don't Fix It: Ancient Computers in Use Today|website=PCWorld|access-date=October 11, 2021}} The Stromasys CHARON-VAX and SIMH software-based VAX emulators remain available. VMS is now developed by VMS Software Incorporated, albeit only for the Alpha, HPE Integrity, and x86-64 platforms.

Processor architecture

File:Microvax 3600 (2).jpg

role="presentation" style="font-size:88%;border: 1px solid #a2a9b1; border-spacing: 3px; background-color: #f8f9fa; color: black; margin: 0.5em 0 0.5em 1em; padding: 0.2em; float: right; clear: right;"
+ DEC VAX registers
{\| style="font-size:88%;width:39em;"
style="width:10px; text-align:left" \| ³₁ \| style="width:60px; text-align:center"\| ... \| style="width:10px; text-align:right" \| ²₃ \| style="width:60px; text-align:center"\| ... \| style="width:10px; text-align:center"\| ¹₅ \| style="width:60px; text-align:center"\| ... \| style="width:10px; text-align:center"\| ⁰₇ \| style="width:60px; text-align:center"\| ... \| style="width:10px; text-align:center"\| ⁰₀ \| style="width:100px; background:white; color:black" \| (bit position)
colspan="10" style="text-align:left;" \| General registers
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R0 \| style="background:white; color:black" colspan="3"\| Register 0
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R1 \| style="background:white; color:black"\| Register 1
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R2 \| style="background:white; color:black"\| Register 2
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R3 \| style="background:white; color:black"\| Register 3
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R4 \| style="background:white; color:black"\| Register 4
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R5 \| style="background:white; color:black"\| Register 5
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R6 \| style="background:white; color:black"\| Register 6
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R7 \| style="background:white; color:black"\| Register 7
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R8 \| style="background:white; color:black"\| Register 8
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R9 \| style="background:white; color:black"\| Register 9
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R10 \| style="background:white; color:black"\| Register 10
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R11 \| style="background:white; color:black"\| Register 11
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R12 / AP \| style="background:white; color:black"\| Register 12 / Argument Pointer
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R13 / FP \| style="background:white; color:black"\| Register 13 / Frame Pointer
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R14 / SP \| style="background:white; color:black"\| Register 14 / Stack Pointer
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| R15 / PC \| style="background:white; color:black"\| Register 15 / Program Counter
colspan="10" style="text-align:left;" \| Processor Status Longword
style="background:silver;color:black" \| style="text-align:center" colspan="9"\| (See adjacent table for bit definitions) \| style="background:white; color:black"\| PSL

role="presentation" style="font-size:88%;border: 1px solid #a2a9b1; border-spacing: 3px; background-color: #f8f9fa; color: black; margin: 0.5em 0 0.5em 1em; padding: 0.2em; float: right; clear: right;"

+ DEC VAX registers

{| style="font-size:88%;width:39em;"

style="width:10px; text-align:left" | ³₁

| style="width:60px; text-align:center"| ...

| style="width:10px; text-align:right" | ²₃

| style="width:60px; text-align:center"| ...

| style="width:10px; text-align:center"| ¹₅

| style="width:60px; text-align:center"| ...

| style="width:10px; text-align:center"| ⁰₇

| style="width:60px; text-align:center"| ...

| style="width:10px; text-align:center"| ⁰₀

| style="width:100px; background:white; color:black" | (bit position)

colspan="10" style="text-align:left;" | General registers