Very-large-scale integration

{{Short description|Creating an integrated circuit by combining many transistors into a single chip}}

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining millions or billions of MOS transistors onto a single chip. VLSI began in the 1970s when MOS integrated circuit (metal oxide semiconductor) chips were developed and then widely adopted, enabling complex semiconductor and telecommunications technologies. The microprocessor and memory chips are VLSI devices.

Before the introduction of VLSI technology, most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI enables IC designers to add all of these into one chip.

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History

= Background =

The history of the transistor dates to the 1920s when several inventors attempted devices that were intended to control current in solid-state diodes and convert them into triodes. Success came after World War II, when the use of silicon and germanium crystals as radar detectors led to improvements in fabrication and theory. Scientists who had worked on radar returned to solid-state device development. With the invention of the first transistor at Bell Labs in 1947, the field of electronics shifted from vacuum tubes to solid-state devices.{{Cite journal |last=Zorpette |first=Glenn |date=20 November 2022 |title=How the First Transistor Worked |url=https://spectrum.ieee.org/transistor-history |journal=IEEE Spectrum}}

With the small transistor at their hands, electrical engineers of the 1950s saw the possibilities of constructing far more advanced circuits. However, as the complexity of circuits grew, problems arose. One problem was the size of the circuit. A complex circuit like a computer was dependent on speed. If the components were large, the wires interconnecting them must be long. The electric signals took time to go through the circuit, thus slowing the computer.{{Cite web |title=The History of the Integrated Circuit |url=https://www.nobelprize.org/educational/physics/integrated_circuit/history/ |url-status=dead |archive-url=https://web.archive.org/web/20180629102838/https://www.nobelprize.org/educational/physics/integrated_circuit/history/ |archive-date=29 Jun 2018 |access-date=21 Apr 2012 |publisher=Nobelprize.org}}

The invention of the integrated circuit by Jack Kilby and Robert Noyce solved this problem by making all the components and the chip out of the same block (monolith) of semiconductor material.{{Cite web |title=BBC - History - Historic Figures: Kilby and Noyce (1923-2005) |url=https://www.bbc.co.uk/history/historic_figures/kilby_and_noyce.shtml |access-date=2024-08-10 |website=www.bbc.co.uk |language=en-GB}} The circuits could be made smaller, and the manufacturing process could be automated. This led to the idea of integrating all components on a single-crystal silicon wafer, which led to small-scale integration (SSI) in the early 1960s, and then medium-scale integration (MSI) in the late 1960s.{{Citation |last=O’Regan |first=Gerard |title=The Invention of the Integrated Circuit and the Birth of Silicon Valley |date=2016 |work=Introduction to the History of Computing: A Computing History Primer |pages=93–100 |editor-last=O'Regan |editor-first=Gerard |url=https://doi.org/10.1007/978-3-319-33138-6_7 |access-date=2024-08-10 |series=Undergraduate Topics in Computer Science |place=Cham |publisher=Springer International Publishing |language=en |doi=10.1007/978-3-319-33138-6_7 |isbn=978-3-319-33138-6|url-access=subscription }}

= VLSI =

General Microelectronics introduced the first commercial MOS integrated circuit in 1964.{{Cite web |title=1964: First Commercial MOS IC Introduced |url=http://www.computerhistory.org/semiconductor/timeline/1964-Commecial.html |website=Computer History Museum}} In the early 1970s, MOS integrated circuit technology allowed the integration of more than 10,000 transistors in a single chip.{{Cite journal |last=Hittinger |first=William C. |date=1973 |title=Metal-Oxide-Semiconductor Technology |journal=Scientific American |volume=229 |issue=2 |pages=48–59 |bibcode=1973SciAm.229b..48H |doi=10.1038/scientificamerican0873-48 |issn=0036-8733 |jstor=24923169}} This paved the way for VLSI in the 1970s and 1980s, with tens of thousands of MOS transistors on a single chip (later hundreds of thousands, then millions, and now billions).

The first semiconductor chips held two transistors each. Subsequent advances added more transistors, and as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as small-scale integration (SSI), improvements in technique led to devices with hundreds of logic gates, known as medium-scale integration (MSI). Further improvements led to large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far past this mark and today's microprocessors have many millions of gates and billions of individual transistors.

At one time, there was an effort to name and calibrate various levels of large-scale integration above VLSI. Terms like ultra-large-scale integration (ULSI) were used. But the huge number of gates and transistors available on common devices has rendered such fine distinctions moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use.

In 2008, billion-transistor processors became commercially available. This became more commonplace as semiconductor fabrication advanced from the then-current generation of 65 nm processors. Current designs, unlike the earliest devices, use extensive design automation and automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic functionality. Certain high-performance logic blocks, like the SRAM (static random-access memory) cell, are still designed by hand to ensure the highest efficiency.{{Citation needed|date=August 2020|reason=This claim needs a reliable source. All online sources which seem to hint to this seem to have copied straight from this Wikipedia article}}

Structured design

Structured VLSI design is a modular methodology originated by Carver Mead and Lynn Conway for saving microchip area by minimizing the interconnect fabric area. This is obtained by repetitive arrangement of rectangular macro blocks which can be interconnected using wiring by abutment. An example is partitioning the layout of an adder into a row of equal bit slices cells. In complex designs this structuring may be achieved by hierarchical nesting.{{Cite book |last=Jain |first=B. K. |url=https://books.google.com/books?id=R5XBozPiTHAC&q=structured%20vlsi%20design%20hierarchical%20nesting&pg=PA159 |title=Digital Electronics - A Modern Approach by B K Jain |date=August 2009 |publisher=Global Vision Publishing House |isbn=9788182202153 |access-date=2 May 2017}}

Structured VLSI design had been popular in the early 1980s, but lost its popularity later{{Citation needed|date = November 2019}} because of the advent of placement and routing tools wasting a lot of area by routing, which is tolerated because of the progress of Moore's law. When introducing the hardware description language KARL in the mid-1970s, Reiner Hartenstein coined the term "structured VLSI design" (originally as "structured LSI design"), echoing Edsger Dijkstra's structured programming approach by procedure nesting to avoid chaotic spaghetti-structured programs.

Difficulties

As microprocessors become more complex due to technology scaling, microprocessor designers have encountered several challenges which force them to think beyond the design plane, and look ahead to post-silicon:

Process variation – As photolithography techniques get closer to the fundamental laws of optics, achieving high accuracy in doping concentrations and etched wires is becoming more difficult and prone to errors due to variation. Designers now must simulate across multiple fabrication process corners before a chip is certified ready for production, or use system-level techniques for dealing with effects of variation.{{Cite book |last1=Wu |first1=Qiang |title=2020 China Semiconductor Technology International Conference (CSTIC) |last2=Li |first2=Yanli |last3=Yang |first3=Yushu |last4=Chen |first4=Shoumian |last5=Zhao |first5=Yuhang |date=2020-06-26 |publisher=IEEE |isbn=978-1-7281-6558-5 |pages=1–6 |chapter=The Law that Guides the Development of Photolithography Technology and the Methodology in the Design of Photolithographic Process |doi=10.1109/CSTIC49141.2020.9282436 |chapter-url=https://ieeexplore.ieee.org/document/9282436}}{{Cite web |title=Exploring the Challenges of VLSI Design: Navigating Complexity for Success |url=https://insemitech.com/blogs/exploring-the-challenges-of-vlsi-design-navigating-complexity-for-success/ |access-date=2024-08-10 |website=InSemi Tech |language=en-US}}
Stricter design rules – Due to lithography and etch issues with scaling, design rule checking for layout has become increasingly stringent. Designers must keep in mind an ever increasing list of rules when laying out custom circuits. The overhead for custom design is now reaching a tipping point, with many design houses opting to switch to electronic design automation (EDA) tools to automate their design process.{{Cite book |last1=Wang |first1=Laung-Terng |url=https://dl.acm.org/doi/10.5555/2843514 |title=Electronic Design Automation: Synthesis, Verification, and Test |last2=Chang |first2=Yao-Wen |last3=Cheng |first3=Kwang-Ting (Tim) |date=February 2009 |publisher=Morgan Kaufmann Publishers Inc. |isbn=978-0-08-092200-3 |location=San Francisco, CA, USA}}
Timing/design closure – As clock frequencies tend to scale up, designers are finding it more difficult to distribute and maintain low clock skew between these high frequency clocks across the entire chip. This has led to a rising interest in multicore and multiprocessor architectures, since an overall speedup can be obtained even with lower clock frequency by using the computational power of all the cores.{{Cite web |date=2024-06-23 |title=Clock Skew in STA |url=https://vlsiweb.com/clock-skew/ |access-date=2024-08-10 |language=en-GB}}
First-pass success – As die sizes shrink (due to scaling), and wafer sizes go up (due to lower manufacturing costs), the number of dies per wafer increases, and the complexity of making suitable photomasks goes up rapidly. A mask set for a modern technology can cost several million dollars. This non-recurring expense deters the old iterative philosophy involving several "spin-cycles" to find errors in silicon, and encourages first-pass silicon success. Several design philosophies have been developed to aid this new design flow, including design for manufacturing (DFM), design for test (DFT), and Design for X.{{Cite journal |last=Rieger |first=Michael L. |date=2019-11-26 |title=Retrospective on VLSI value scaling and lithography |url=https://www.spiedigitallibrary.org/journals/journal-of-micro-nanolithography-mems-and-moems/volume-18/issue-04/040902/Retrospective-on-VLSI-value-scaling-and-lithography/10.1117/1.JMM.18.4.040902.full |journal=Journal of Micro/Nanolithography, MEMS, and MOEMS |volume=18 |issue=4 |page=040902 |bibcode=2019JMM&M..18d0902R |doi=10.1117/1.JMM.18.4.040902 |issn=1932-5150}}
Electromigration

References

External links

[http://scale.engin.brown.edu/classes/EN1600S08/ Lectures on Design and Implementation of VLSI Systems at Brown University]
[https://web.archive.org/web/20031223071416/http://lsiwww.epfl.ch/LSI2001/teaching/webcourse/toc.html Design of VLSI Systems]

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Category:Integrated circuits

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