Virtex (FPGA)#Virtex-E

The Virtex series of FPGAs are based on Configurable Logic Blocks (CLBs), where each CLB is equivalent to multiple ASIC gates.[https://books.google.com/books?id=FD2JDc7CpSgC&dq=virtex+logic+blocks&pg=PA513 Field Programmable Logic and Applications], Springer Science & Business Media, 21-Aug-2002[https://books.google.com/books?id=5ZlAAAAAQBAJ&dq=virtex+logic+blocks&pg=PA713 Handbook of Signal Processing Systems - Volume 2], Springer Science & Business Media, 20-Jun-2013 Each CLB is composed of multiple slices, that differ in construction between Virtex families.

Virtex FPGAs include an I/O Block for controlling input/output pins on the Virtex chip, that support a variety of signalling standards.[https://books.google.com/books?id=6L5TXxyfl4UC&dq=virtex+logic+blocks&pg=PA49 Cryptographic Hardware and Embedded Systems], Springer Science & Business Media, 02-Sep-2003 All pins default to "input" mode (high impedance). I/O pins are grouped into I/O Banks, where each Bank can support a different voltage.

In addition to configurable FPGA logic, Virtex FPGAs include fixed-function hardware for multipliers, memories, microprocessor cores, FIFO and ECC logic, DSP blocks, PCI Express controllers, Ethernet MAC blocks, and high-speed serial transceivers.Ron Wilson, EDN. "[http://www.edn.com/article/459148-Xilinx_FPGA_introductions_hint_at_new_realities.php Xilinx FPGA introductions hint at new realities] {{Webarchive|url=https://web.archive.org/web/20110525031230/http://www.edn.com/article/459148-Xilinx_FPGA_introductions_hint_at_new_realities.php |date=2011-05-25 }}." February 2, 2009 Retrieved June 10, 2010.Design & Reuse. "[http://www.design-reuse.com/news/19988/xilinx-virtex-6-fpga.html New Xilinx Virtex-6 FPGA Family Designed to Satisfy Insatiable Demand for Higher Bandwidth and Lower Power Systems]." February 2, 2009. Retrieved June 10, 2010.

Some Virtex family members (such as the Virtex-5QX) are available in radiation-hardened packages, for outer-space applications.Don Clark, Wall Street Journal. "[https://blogs.wsj.com/digits/2010/07/19/xilinx-say-new-chips-adept-at-surviving-space-radiation/?KEYWORDS=Xilinx+Says+New+Chips+Adept+at+Surviving+Space+Radiation Xilinx Say New Chips Adept at Surviving Space Radiation.]" July 19, 2010. Retrieved August 10, 2010.

The Virtex-E family was introduced in September 1999 on a 180 nm process technology.{{cite web|url=http://edgar.secdatabase.com/1862/101287001501165/filing-main.htm |title=Xilinx Inc, Form 10-K, Annual Report, Filing Date Jun 12, 2001 |publisher=secdatabase.com |access-date =May 6, 2018}} Virtex-E includes a two million system gate device and supports twice the system-gate density and has a 50 percent higher I/O performance than the original Virtex FPGAs.{{cite web|url=http://edgar.secdatabase.com/2528/104746904019430/filing-main.htm |title=Xilinx Inc, Form 10-K, Annual Report, Filing Date Jun 4, 2004 |publisher=secdatabase.com |access-date =May 6, 2018}}

Xilinx introduced Virtex-II family in January 2001 on 150 nm process technology,{{cite web|url=http://edgar.secdatabase.com/1862/101287001501165/filing-main.htm |title=Xilinx Inc, Form 10-K, Annual Report, Filing Date Jun 12, 2001 |publisher=secdatabase.com |access-date =May 6, 2018}} and Virtex-II Pro family in March 2002 on 90 nm process technology.{{cite web|url=http://edgar.secdatabase.com/2603/101287002002739/filing-main.htm |title=Xilinx Inc, Form 10-K, Annual Report, Filing Date Jun 17, 2002 |publisher=secdatabase.com |access-date =May 6, 2018}} The Virtex-II and Virtex-II Pro families are considered legacy devices, and are not recommended for use in new designs, although they are still produced by Xilinx for existing designs.

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The Virtex-4 family are considered legacy devices, and are not recommended for use in new designs, although they are still produced by Xilinx for existing designs.

Virtex-4 family was introduced in June 2004 on 90 nm process technology.{{cite web|url=http://edgar.secdatabase.com/669/104746905016238/filing-main.htm |title=Xilinx Inc, Form 10-K, Annual Report, Filing Date Jun 1, 2005 |publisher=secdatabase.com |access-date =May 6, 2018}}{{cite web|url=http://pdf.secdatabase.com/1492/0001104659-04-031400.pdf |title=Xilinx Inc, Form 8-K, Current Report, Filing Date Oct 21, 2004 |publisher=secdatabase.com |access-date =May 6, 2018}} Virtex-4 FPGAs have been used for the ALICE (A Large Ion Collider Experiment) at the CERN European laboratory on the French-Swiss border to map and disentangle the trajectories of thousands of subatomic particles.Xcell Journal, "[http://www.xilinx.com/publications/xcellonline/xcell_65/xc_pdf/p28_31_65_F_XiWild.pdf CERN Scientists Use Virtex-4 FPGAs for Big Bang Research] {{Webarchive|url=https://web.archive.org/web/20090327150946/http://www.xilinx.com/publications/xcellonline/xcell_65/xc_pdf/p28_31_65_F_XiWild.pdf |date=2009-03-27 }}." July 2008. Retrieved January 28, 2009.

The Virtex-5 family was introduced in May 2006 on 65 nm process technology.{{cite web|url=http://edgar.secdatabase.com/822/110465906049057/filing-main.htm |title=Xilinx Inc, Form 8-K, Current Report, Filing Date Jul 26, 2006 |publisher=secdatabase.com |access-date =May 6, 2018}} The Virtex-5 LX and the LXT are intended for logic-intensive applications, and the Virtex-5 SXT is for DSP applications.DSP DesignLine. "[http://www.industrialcontroldesignline.com/products/208404026' Analysis: Xilinx debuts Virtex-5 FXT, expands SXT]." June 13, 2008. Retrieved January 20, 2008. With the Virtex-5, Xilinx changed the logic fabric from four-input LUTs to six-input LUTs. With the increasing complexity of combinational logic functions required by SoC designs, the percentage of combinational paths requiring multiple four-input LUTs had become a performance and routing bottleneck. The new six-input LUT represented a tradeoff between better handling of increasingly complex combinational functions, at the expense of a reduction in the absolute number of LUTs per device. The Virtex-5 series is a 65 nm design fabricated in 1.0 V, triple-oxide process technology.{{cite web|url=http://edgar.secdatabase.com/2628/104746906007867/filing-main.htm |title=Xilinx Inc, Form 10-K, Annual Report, Filing Date May 31, 2006 |publisher=secdatabase.com |access-date =May 6, 2018}}National Instruments. "[http://zone.ni.com/devzone/cda/tut/p/id/7440#toc1 Advantages of the Xilinx Virtex-5 FPGA]." June 17, 2009. Retrieved June 29, 2010.

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The Virtex-6 family was introduced in February 2009 on a 40 nm process technology for compute-intensive electronic systems,{{cite web|url=http://edgar.secdatabase.com/1217/120677409001145/filing-main.htm |title=Xilinx Inc, Form 10-K, Annual Report, Filing Date Jun 1, 2009 |publisher=secdatabase.com |access-date =May 6, 2018}} and the company claims it consumes 15 percent less power and has 15 percent improved performance over competing 40 nm FPGAs.Company Release. "[https://archive.today/20120713091646/http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1250609&highlight= New Xilinx Virtex-6 FPGA Family Designed to Satisfy Insatiable Demand for Higher Bandwidth and Lower Power Systems]." February 2, 2009. Retrieved February 2, 2009.

The Virtex-7 family was introduced in June 2010 on a 28 nm process technology,{{cite web|url=http://edgar.secdatabase.com/1249/95012311055454/filing-main.htm |title=Xilinx Inc, Form 10-K, Annual Report, Filing Date May 31, 2011 |publisher=secdatabase.com |access-date =May 6, 2018}} and is reported to deliver a two-fold system performance improvement at 50 percent lower power compared to previous generation Virtex-6 devices.{{cite web|url=http://edgar.secdatabase.com/2304/95012310066839/filing-main.htm |title=Xilinx Inc, Form 8-K, Current Report, Filing Date Jul 21, 2010 |publisher=secdatabase.com |access-date =May 6, 2018}} In addition, Virtex-7 doubles the memory bandwidth compared to previous generation Virtex FPGAs with 1866 Mbit/s memory interfacing performance and over two million logic cells.EE Times. “[http://press.xilinx.com/2015-11-19-Xilinx-Announces-the-Spartan-7-FPGA-Family Xilinx Announces the Spartan-7 FPGA Family].” Nov 19, 2015. Retrieved February 10, 2015.Kevin Morris, FPGA Journal. “[http://www.techfocusmedia.net/fpgajournal/feature_articles/20100622-virtex/ Veni! Vidi! Virtex! (and Kintex and Artix Too)] {{Webarchive|url=https://web.archive.org/web/20101123043600/http://www.techfocusmedia.net/fpgajournal/feature_articles/20100622-virtex/ |date=2010-11-23 }}.” June 21, 2010. Retrieved September 23, 2010.

In 2011, Xilinx began shipping sample quantities of the Virtex-7 2000T FPGA, which combines four smaller FPGAs into a single package by placing them on a special silicon interconnection pad (called an interposer) to deliver 6.8 billion transistors in a single large chip. The interposer provides 10,000 data pathways between the individual FPGAs – roughly 10 to 100 times more than would usually be available on a board – to create a single FPGA.Don Clark, The Wall Street Journal. "[https://blogs.wsj.com/digits/2011/10/25/xilinx-says-four-chips-act-like-one-giant/?KEYWORDS=Xilinx Xilinx Says Four Chips Act Like One Giant]." October 25, 2011. Retrieved November 18, 2011.Clive Maxfield, EETimes. "[http://www.eetimes.com/electronics-news/4230048/Xilinx-announces-world-s-highest-capacity-FPGA Xilinx tips world’s highest capacity FPGA]." October 25, 2011. Retrieved November 18, 2011.David Manners, Electronics Weekly. "[http://www.electronicsweekly.com/Articles/25/10/2011/52110/xilinx-launches-20m-asic-gate-stacked-silicon-fpga.htm Xilinx launches 20m ASIC gate stacked silicon FPGA]." October 25, 2011. Retrieved November 18, 2011. In 2012, using the same 3D technology, Xilinx introduced initial shipments of their Virtex-7 H580T FPGA, a heterogeneous device, so called because it comprises two FPGA dies and one 8-channel 28 Gbit/s transceiver die in the same package.Electronic Product News. "[http://www.epn-online.com/page/new188150/with-moshe-gavrielov-president-ceo-xilinx.html Interview with Moshe Gavrielov, president, CEO, Xilinx]." May 15, 2012. Retrieved June 12, 2012.

As Xilinx introduced new high capacity 3D FPGAs, including Virtex-7 2000T and Virtex-7 H580T products, these devices began to outpace the capacity of Xilinx’s design software, which led the company to completely redesign its tool set. The result was the introduction of the Vivado Design Suite, which reduces the time needed for programmable logic and I/O design, and speeds systems integration and implementation compared to the previous software.EDN. "[http://www.edn.com/electronics-products/other/4375467/The-Vivado-Design-Suite-accelerates-programmable-systems-integration-by-up-to-4X The Vivado Design Suite accelerates programmable systems integration and implementation by up to 4X]." Jun 15, 2012. Retrieved Jan 3, 2013.

The Virtex UltraScale family was introduced in May, 2014 on a 20 nm process technology.{{cite web|url=http://edgar.secdatabase.com/1313/74398815000022/filing-main.htm |title=Xilinx Inc, Form 10-K, Annual Report, Filing Date May 13, 2015 |publisher=secdatabase.com |access-date =May 6, 2018}}http://forums.xilinx.com/t5/Xcell-Daily-Blog/Xilinx-ships-first-20nm-Virtex-UltraScale-FPGA-Why-this-matters/ba-p/458488 {{User-generated source|date=August 2022}} The UltraScale is a "3D FPGA" that contains up to 4.4M logic cells, and uses up to 45% lower power vs. previous generations, and up to 50% lower BOM cost.[http://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale.html Virtex UltraScale], Xilinx

The Virtex UltraScale+ family was introduced in January 2016 on a 16 nm process technology.{{cite web|url=http://edgar.secdatabase.com/2687/74398816000063/filing-main.htm |title=Xilinx Inc, Form 10-K, Annual Report, Filing Date May 17, 2016 |publisher=secdatabase.com |access-date =May 6, 2018}}

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The Virtex-II Pro, Virtex-4, Virtex-5, and Virtex-6 FPGA families, which include up to two embedded IBM PowerPC cores, are targeted to the needs of system-on-chip (SoC) designers.[http://www.xilinx.com/support/documentation/data_sheets/ds083.pdf Virtex-II Pro Datasheet][http://www.xilinx.com/support/documentation/data_sheets/ds112.pdf Virtex-4 Family Overview]Richard Wilson, ElectronicsWeekly.com, "[http://www.electronicsweekly.com/Articles/2009/02/02/45377/xilinx-repositions-fpgas-with-soc-move.htm Xilinx repositions FPGAs with SoC move]." February 2, 2009. Retrieved on February 2, 2009.

• List of Xilinx FPGAs

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• Intel (former Altera)
• Lattice Semiconductor

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