Wide-issue

{{primary sources|date=October 2015}}

A wide-issue architecture is a computer processor that issues more than one instruction per clock cycle.{{cite web|title=Scheduling for Superscalar & Multiple Issue Machines|url=http://pages.cs.wisc.edu/~fischer/cs701.f08/lectures/Lecture12.4up.pdf}} They can be considered in three broad types:

• Statically-scheduled superscalar architectures execute instructions in the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle.
• VLIW architectures rely on the programming software (compiler) to determine which instructions to dispatch on a given clock cycle.{{cite web|title=Wide Issue and Speculation|url=http://taco.cse.tamu.edu/utsa-www/cs5513-fall07/lecture6.html}}
• Dynamically-scheduled superscalar architectures execute instructions in an order that gives the same result as the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle.{{cite web|last1=Martin|first1=Milo|title=Superscalar|url=https://www.cis.upenn.edu/~milom/cis501-Fall11/lectures/07_superscalar.pdf}}