Zen 2

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| footer = Two delidded Zen 2 processors designed with the multi-chip module approach. The Ryzen 5 3600 CPU on the left/top (used for mainstream Ryzen CPUs) uses a smaller, less capable I/O die and up to two CCDs (only one is used on this particular example), while the Epyc 7702 on the right/bottom (used for high-end desktop, HEDT, Ryzen Threadripper and server Epyc CPUs) uses a larger, more capable I/O die and up to eight CCDs.

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Zen 2 is a significant departure from the physical design paradigm of AMD's previous Zen architectures, Zen and Zen+. Zen 2 moves to a multi-chip module design where the I/O components of the CPU are laid out on its own die which is separate from the dies containing processor cores, which are also called chiplets in this context. This separation has benefits in scalability and manufacturability. As physical interfaces don't scale very well with shrinks in process technology, their separation into a different die allows these components to be manufactured using a larger, more mature process node than the CPU dies. The CPU dies (referred to by AMD as {{em|core complex dies}} or CCDs), now more compact due to the move of I/O components onto another die, can be manufactured using a smaller process with fewer manufacturing defects than a larger die would exhibit (since the chances of a die having a defect increases with device (die) size) while also allowing for more dies per wafer. In addition, the central I/O die can service multiple chiplets, making it easier to construct processors with a large number of cores.{{cite web |last1=Cutress |first1=Ian |title=AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome |url=https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome |website=AnandTech |page=1 |access-date=17 June 2019 |date=10 June 2019}}{{cite web |last1=De Gelas |first1=Johan |title=AMD Rome Second Generation EPYC Review: 2x 64-core Benchmarked |url=https://www.anandtech.com/show/14694/amd-rome-epyc-2nd-gen/2 |website=AnandTech |access-date=29 September 2019 |date=7 August 2019}}

File:Zen2 Microarchitektur.svg

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| footer = On the left (top on mobile): Die shot of a Zen 2 Core Complex Die. On the middle: Die shot of a Zen 2 EPYC/Threadripper I/O die, On the right (bottom): I/O die of a Zen 2 mainstream Ryzen I/O die.

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With Zen 2, each CPU chiplet houses 8 CPU cores, arranged in 2 {{em|core complexes}} (CCXs), each of 4 CPU cores. These chiplets are manufactured using TSMC's 7 nanometer MOSFET node and are about 74 to 80 mm² in size. The chiplet has about 3.8 billion transistors, while the 12 nm I/O die (IOD) is ~125 mm² and has 2.09 billion transistors.{{Cite web|url=https://www.tomshardware.com/reviews/ryzen-9-3900x-7-3700x-review,6214.html|title=AMD Ryzen 9 3900X and Ryzen 7 3700X Review: Zen 2 and 7nm Unleashed|first=Paul Alcorn 21|last=November 2019|website=Tom's Hardware|date=21 November 2019}} The amount of L3 cache has been doubled to 32 MB, with each CCX in the chiplet now having access to 16 MB of L3 compared to the 8 MB of Zen and Zen+.{{cite web |last1=Cutress |first1=Ian |title=AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome |url=https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome/2 |website=AnandTech |access-date=17 June 2019 |date=10 June 2019}} AVX2 performance is greatly improved by an increase in execution unit width from 128-bit to 256-bit.{{cite web |last1=Cutress |first1=Ian |title=AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome |url=https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome/9 |website=AnandTech |access-date=17 June 2019 |date=10 June 2019}} There are multiple variants of the I/O die: one manufactured on GlobalFoundries 14 nanometer process, and another manufactured using the same company's 12 nanometer process. The 14 nanometer dies have more features and are used for the EPYC Rome processors, whereas the 12 nm versions are used for consumer processors. Both processes have similar feature sizes, so their transistor density is also similar.{{Cite web|url=https://fuse.wikichip.org/news/1497/vlsi-2018-globalfoundries-12nm-leading-performance-12lp/|title=VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP|first=David|last=Schor|date=22 July 2018}}

AMD's Zen 2 architecture can deliver higher performance at a lower power consumption than Intel's Cascade Lake architecture, with an example being the AMD Ryzen Threadripper 3970X running with a TDP of 140{{nbsp}}W in ECO mode delivering higher performance than the Intel Core i9-10980XE running with a TDP of 165{{nbsp}}W.{{Cite web|url=https://wccftech.com/amd-ryzen-threadripper-3970x-32-core-efficient-monster-cpu-eco-mode-tests/|title=AMD Ryzen Threadripper 3970X Is An Absolutely Efficient Monster CPU|first=Hassan|last=Mujtaba|date=24 December 2019}}

• Some new instruction set extensions: WBNOINVD, CLWB, RDPID, RDPRU, MCOMMIT. Each instruction uses its own CPUID bit.{{Cite web|url=https://www.phoronix.com/scan.php?page=news_item&px=AMD-Zen-2-New-Instructions|title=AMD Zen 2 CPUs Come With A Few New Instructions - At Least WBNOINVD, CLWB, RDPID - Phoronix|website=www.phoronix.com}}{{Cite web|url=https://www.phoronix.com/scan.php?page=news_item&px=GNU-Binutils-Zen-2-Bits|title=GNU Binutils Adds Bits For AMD Zen 2's RDPRU + MCOMMIT Instructions - Phoronix|website=www.phoronix.com}}
• Hardware mitigations against the Spectre V4 speculative store bypass vulnerability.{{cite news|url=https://www.techpowerup.com/256478/amd-zen-2-has-hardware-mitigation-for-spectre-v4|last=btarunr|website=TechPowerUp|title=AMD Zen 2 has Hardware Mitigation for Spectre V4|date=12 June 2019|access-date=18 October 2019}}
• Zero-latency memory mirroring optimization (undocumented).{{cite web |last1=Agner |first1=Fog |title=Surprising new feature in AMD Ryzen 3000 |url=https://www.agner.org/forum/viewtopic.php?f=1&t=41 |website=Agner's CPU blog|author-link=Agner Fog}}
• Doubled width of the execution units and load store units (from 128-bit to 256-bit) in the floating point coprocessor and significant further throughput enhancements in the multiplication execution unit. This allows the FPU to perform single-cycle AVX2 calculations.{{Cite web |last=Cutress |first=Ian |url=https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome/9 |title=AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome |date=10 June 2019 |access-date=12 January 2023 |website=AnandTech}}

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APU features table

On 26 May 2019, AMD announced six Zen 2-based desktop Ryzen processors (codenamed "Matisse"). These included 6-core and 8-core variants in the Ryzen 5 and Ryzen 7 product lines, as well as a new Ryzen 9 line that includes the company's first 12-core and 16-core mainstream desktop processors. {{cite web |last1=Cutress |first1=Ian |title=AMD Ryzen 3000 Announced: Five CPUs, 12 Cores for $499, Up to 4.6 GHz, PCIe 4.0, Coming 7/7 |url=https://www.anandtech.com/show/14407/amd-ryzen-3000-announced-five-cpus-12-cores-for-499-up-to-46-ghz-pcie-40-coming-77 |website=AnandTech |access-date=17 June 2019 |date=26 May 2019}}

The Matisse I/O die is also used as the X570 chipset.

AMD's second generation of Epyc processors, codenamed "Rome", feature up to 64 cores, and were launched on 7 August 2019.

{{AMD Ryzen 3000 Series}}

{{AMD Ryzen Threadripper 3000 series}}

Based on the Ryzen 4000G series APUs but with the integrated graphics disabled.

{{AMD Ryzen 4000 series}}

Initially only provided to OEM; later, AMD released retail Zen 2 desktop APUs in April 2022.https://www.techpowerup.com/cpu-specs/ryzen-5-4600g.c2319

{{AMD Ryzen 4000G series}}

{{AMD Ryzen Mobile 4000 series}}

{{AMD Ryzen Mobile 5000 Zen 2 based series}}

In 2022, AMD announced the Mendocino ultra-mobile APUs.{{Cite web|url=https://www.tomshardware.com/news/amd-ryzen-athlon-7020-apu-specs-mendocino|title=AMD Details 7020 Series Ryzen and Athlon 'Mendocino' Mobile APUs|date=20 September 2022|website=Tom's Hardware}}

{{AMD Ryzen Mobile 7020 series}}

{{AMD Ryzen Embedded V2000 Series}}

{{AMD Epyc 7002 series}}

• Xbox Series X and Series S
• PlayStation 5
• Steam Deck
• AMD 4700S{{cite web |title= AMD 4700S 8-Core Processor Desktop Kit |url=https://www.amd.com/en/desktop-kits/amd-4700s |website=AMD |access-date=26 September 2022}}

AMD Ryzen 7 3700X top IMGP3165 smial wp.jpg|AMD Ryzen 7 3700X

AMD@7nm(12nmIOD)@Zen2@Matisse@Ryzen 5 3600@100-000000031 BF 1923SUT 9HM6935R90062 DSC04789-DSC04810 - ZS-DMap (48319202011).jpg|Zen 2 I/O Die

AMD@7nm(12nmIO)@Zen2@Matisse@Ryzen 5 3600@100-000000031 BF 1923SUT 9HM6935R90062 DSCx4@IOD Infrared.jpg|Infrared die shot of the I/O Die

AMD EPYC Rome 12nm IO die shot 3.jpg|EPYC I/O Die

Zen2 Matisse Ryzen 7nm Core Die shot.jpg|Zen 2 Core Complex Die (CCD)

AMD@7nm(12nmIOD)@Zen2@Rome@EPYC 7702 ES@2S1404E2VJUG5 BB ES DSCx1.jpg|AMD EPYC 7702 server processor

AMD@7nm(12nmIOD)@Zen2@Rome@EPYC 7702 ES@2S1404E2VJUG5 BB ES DSCx3.jpg|A delidded AMD 7702 featuring 8 CCDs and 1 I/O die, with remains of the solder thermal interface material (TIM) on the chiplets

{{Commons category|Zen 2 microarchitecture}}

• Jim Keller (engineer)
• Manycore processor

{{reflist}}

{{AMD processors}}

{{AMD processor roadmap}}

Category:AMD microarchitectures

Category:AMD x86 microprocessors

Category:X86 microarchitectures

Category:Computer-related introductions in 2019