back-side bus
{{Short description|Computer architecture terminology}}
In personal computer microprocessor architecture, a back-side bus (BSB), or backside bus, was a computer bus used on early Intel platforms to connect the CPU to CPU cache memory, usually off-die L2. If a design utilizes a back-side bus along with a front-side bus (FSB), the design is said to use a dual-bus architecture, or in Intel's terminology Dual Independent Bus (DIB){{cite web|url=http://www.pcguide.com/ref/cpu/arch/extBackside-c.html|title=Dedicated Backside Cache Bus|publisher=PCguide.com|date=2001-04-30}} architecture. The back-side bus architecture evolved when newer processors like the second-generation Pentium III began to incorporate on-die L2 cache, which at the time was advertised as Advanced Transfer Cache, but Intel continued to refer to the Dual Independent Bus till the end of Pentium III.[http://download.intel.com/design/intarch/prodbref/27331106.pdf Pentium® III Processors for Applied Computing product brief]
History
BSB is an improvement over the older practice of using a single system bus, because a single bus typically became a severe bottleneck as CPUs and memory speeds increased. Due to its dedicated nature, the back-side bus can be optimized for communication with cache, thus eliminating protocol overheads and additional signals that are required on a general-purpose bus. Furthermore, since a BSB operates over a shorter distance, it can typically operate at higher clock speeds, increasing the computer's overall performance.
Cache connected with a BSB was initially external to the microprocessor die, but now is usually on-die.{{cite web |url= http://www.itworld.com/Comp/1091/CWD010430STO60015/ |archiveurl= https://web.archive.org/web/20010502134148/http://www.itworld.com/Comp/1091/CWD010430STO60015/ |archivedate= 2001-05-02|
title=Buses: frontside and backside|
publisher=ITworld|
date=2001-04-30}} In the latter case, the BSB clock frequency is typically equal to the processor's,{{cite web|
url=http://www.itworld.com/Comp/1091/CWD010430STO60015/|
archiveurl=https://web.archive.org/web/20010502134148/http://www.itworld.com/Comp/1091/CWD010430STO60015/|
archivedate=2001-05-02|
title=Buses: frontside and backside|
publisher=ITworld|
date=2001-04-30}} and the back-side bus can also be made much wider (256-bit, 512-bit) than either off-chip or on-chip FSB.{{Clarify|reason=What is "on-chip FSB" and how does it differ from "off-chip FSB"? Aren't all FSBs made for off-chip communicatio?|date=July 2022}}
File:P2 Deschutes open front.jpg
The dual-bus architecture was used in a number of designs, including the IBM and Freescale (formerly the semiconductor division of Motorola) PowerPC processors (certain PowerPC 604 models, the PowerPC 7xx family,{{cite web|url=http://news.cnet.com/Monday+a+big+day+for+Apple/2100-1001_3-205119.html|title=Monday a big day for Apple|publisher=CNet|date=1997-11-07}} and the Freescale 7xxx line), as well as the Intel Pentium Pro, Pentium II and early Pentium III processors,{{cite web|
url=http://searchstorage.techtarget.com/sDefinition/0,,sid5_gci213804,00.html|
title=Backside Bus|
publisher=Whatis.com|
date=2001-04-30}}
which used it to access their L2 cache (earlier Intel processors accessed the L2 cache over the FSB, while later processors moved it on-chip).