bit-serial architecture
{{Short description|Computational system in which data are sent one bit at a time down a wire}}
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In computer architecture, bit-serial architectures send data one bit at a time, along a single wire, in contrast to bit-parallel word architectures, in which data values are sent all bits or a word at once along a group of wires.
All digital computers built before 1951, and most of the early massive parallel processing machines used a bit-serial architecture—they were serial computers.
Bit-serial architectures were developed for digital signal processing in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation.
The HP Nut processor used in many Hewlett-Packard calculators operated bit-serially.
Assuming N is an arbitrary integer number, N serial processors will often take less FPGA area and have a higher total performance than a single N-bit parallel processor.
See also
References
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{{cite book |title=VLSI signal processing: a bit-serial approach |series=VLSI systems series |author-first1=Peter B. |author-last1=Denyer |author-link1=Peter B. Denyer |author-first2=David |author-last2=Renshaw |publisher=Addison-Wesley |date=1985 |isbn=978-0-201-13306-6 |url=https://books.google.com/books?id=EklTAAAAMAAJ}}
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External links
- [http://portal.acm.org/citation.cfm?id=503063 Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method]
- [http://portal.acm.org/citation.cfm?id=741014 BIT-Serial FIR filters with CSD Coefficients for FPGAs]
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