four-phase logic

Four-phase logic is a type of, and design methodology for dynamic logic. It enabled non-specialist engineers to design quite complex ICs, using either PMOS or NMOS processes.

It uses a kind of 4-phase clock signal.

History

R. K. "Bob" Booher, an engineer at Autonetics, invented four-phase logic and communicated the idea to Frank Wanlass at Fairchild Semiconductor; Wanlass promoted this logic form at General Instrument Microelectronics Division.

{{cite book

| title = To the Digital Age: Research Labs, Start-up Companies, and the Rise of MOS Technology

| first = Ross Knox |last=Bassett

| publisher = JHU Press

| year = 2007

| isbn = 978-0-8018-8639-3

| pages = 129–130

| url = https://books.google.com/books?id=UUbB3d2UnaAC&pg=PA129

}}

Booher made the first working four-phase chip, the Autonetics DDA integrator, during February 1966; he later designed several chips for and built the Autonetics D200 airborne computer using this technique.{{Cite book |chapter-url=http://www.computer.org/portal/web/csdl/doi/10.1109/AFIPS.1968.126|doi=10.1109/AFIPS.1968.126 |first=R. |last=Booher |chapter=MOS GP Computer |title=Managing Requirements Knowledge, International Workshop on, SAN FRANSISCO[sic] |year=1968 |page=877– }}

In April 1967, Joel Karp and Elizabeth de Atley published an article, "Use four-phase MOS IC logic" in Electronic Design magazine.

{{cite journal |last1=Karp |first1=J. |last2=DeAtley |first2=E. |title=Use four-phase MOS IC logic |journal=Electronic Design |volume=15 |issue=7 |pages=62–66 |date=1967 |doi= |url=}}
{{cite book

| title = Exposing electronics

| year = 2000

| isbn = 978-90-5823-057-7

| page = 133

| url = https://books.google.com/books?id=lXA2ObkPNQoC&pg=PA133

}}

In the same year, Cohen, Rubenstein, and Wanlass published "MTOS four phase clock systems."

{{citation

| work = Northeast Electronics Research and Engineering Meeting (NEREM) Record

| date = 1–3 Nov 1967

| volume = 9

| pages = 170–1

}}

Wanlass had been director of research and engineering at General Instrument Microelectronics Division in New York since leaving Fairchild Semiconductor in 1964.

Lee Boysel, a disciple of Wanlass

{{cite book

| title = To the Digital Age: Research Labs, Start-up Companies, and the Rise of MOS Technology

| first = Ross Knox |last=Bassett

| publisher = JHU Press

| year = 2007

| isbn = 978-0-8018-8639-3

| page = 122

| url = https://books.google.com/books?id=UUbB3d2UnaAC&pg=PA122

}}

and a designer at Fairchild Semiconductor, and later founder of Four-Phase Systems, gave a "late news" talk on a four-phase 8-bit adder device in October 1967 at the International Electron Devices meeting.

{{citation

| work = International Electron Devices Meeting (IEDM)

| title = MOS/LSI 8-Bit Parallel Accumulator

| volume = 15

| issue = 6

| date = Oct 1967

| bibcode = 1968ITED...15..410B

| doi = 10.1109/T-ED.1968.16205

}}

J. L. Seely, manager of MOS Operations at General Instrument Microelectronics Division, also wrote about four-phase logic in late 1967.

{{cite journal

| journal = Solid State Technology

| title = Advances in the state-of-the-art of MOS device technology

| first = J.L. |last=Seely

| volume = 10

| pages = 55–62

| date = March 1967

| url = https://books.google.com/books?id=RIxUAAAAMAAJ&q=%22J.+L.+Seely%22+%22four-phase%22

| isbn = 9780070231498

}}

In 1968 Boysel published an article "Adder on a Chip: LSI Helps Reduce Cost of Small Machine" in Electronics magazine;

{{cite journal

| journal = Electronics

| title = Adder on a Chip: LSI Helps Reduce Cost of Small Machine

| first = Lee L. |last=Boysel

| volume = 41 |issue=6 |issn=0013-5070

| pages = 119–123

| date = 18 March 1968

}}

Four-phase papers from Y. T. Yen also appeared that year.

{{cite journal |first=Y.T. |last=Yen |title=A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation |journal=IEEE Transactions on Computers |page=C-17 |date=September 1968 |issue=9 |doi=10.1109/TC.1968.229140 |s2cid=27138705 }}

{{cite journal |first=Y.T. |last=Yen |title=Intermittent Failure Problems of Four-Phase MOS Circuits |journal=IEEE Journal of Solid-State Circuits |volume=SC-4 |issue=3 |date=June 1969 |pages=107–110 |doi=10.1109/JSSC.1969.1049972 |bibcode=1969IJSSC...4..107. }}

Other papers followed shortly.

{{cite journal |last1=Hatt |first1=R.J. |last2=Jackets |first2=A.E. |last3=Jarvis |first3=D.B. |title=Four-phase Logic Circuits using Integrated m-o-s Transistors |journal=Mullard Technical Communication |issue=99 |date=May 1969 |issn=0027-3139 |oclc=2448783}}

Boysel recalls that four-phase dynamic logic allowed him to achieve 10X the packing density, 10X the speed, and 1/10 the power compared to other MOS techniques being used at the time (metal-gate saturated-load PMOS logic), using the first-generation MOS process at Fairchild.{{cite web | url = http://inst-tech.engin.umich.edu/leccap/view/ece-inv-lectures/1036 | title = Making Your First Million (and other tips for aspiring entrepreneurs) | first = Lee |last=Boysel | date = October 12, 2007 | work = U. Mich. EECS Presentation / ECE Recordings | url-status = dead | archiveurl = https://web.archive.org/web/20121115072151/http://inst-tech.engin.umich.edu/leccap/view/ece-inv-lectures/1036 | archivedate = 15 November 2012}}

Structure

There are two types of logic gates – a '1' gate and a '3' gate. These differ only in the clock phases used to drive them. A gate can have any logic function; thus, potentially, every gate has a customized layout. An example 2-input NAND 1 gate and an inverter 3 gate, together with their clock phases (the example uses NMOS transistors), are shown below:

File:4phase.jpg

The Φ1 and Φ3 clocks need to be non-overlapping, as do the Φ2 and Φ4 clocks. Considering the 1 gate, during the Φ1 clock high time (also known as the precharge time), the output C precharges up to V(Φ1)−V_th, where V_th represents the threshold of the precharge transistor. During the next quarter clock cycle (the sample time), when Φ1 is low, and Φ2 is high, C either stays high (if A or B are low) or C gets discharged low (if A and B are high).

The A and B inputs must be stable throughout this sample time. The output C becomes valid during this time – and therefore, a 1 gate output can't drive another 1 gate's inputs. Hence 1 gates have to feed 3 gates, and they, in turn, have to feed 1 gates.

One more thing is useful – 2 and 4 gates. A 2 gate precharges on Φ1 and samples on Φ3:

File:2gate.png

and a 4 gate precharges on Φ3 and samples on Φ1.

Gate interconnection rules are: 1 gates can drive 2 gates and/or 3 gates; 2 gates can drive only 3 gates; 3 gates can drive 4 gates and/or 1 gates; 4 gates can drive only 1 gates:

File:4phase circle.svg

Usage

Four-phase logic works well; in particular, there are no race hazards because every combinational logic gate includes a register. It's worth noting that the layout does not require the bussing of any power supplies – only clock lines are bussed. Also, since the design technique is ratioless (cf. static logic), many designs can use minimum-size transistors.

There are some difficulties:

The gate output is dynamic. This means that its state is held on capacitance at the gate output. But the output track can cross clock lines and other gate outputs, all of which can change the charge on the capacitor. So that the gate output voltage remains at some safe 0 or 1 level during the cycle, the amount of change has to be calculated, and, if necessary, additional (diffusion) capacitance has to be added to the output node.
For a given supply voltage, process, and clock frequency, the designer has to do some calculations so that the layout engineers can, in turn, do their calculations to work out the 'bulk-up' capacitance needed for each gate. A gate with a lot of capacitance load could need bigger than minimum input transistors (so that the load could be discharged in time). This, in turn, increases the load on the gates driving that gate's inputs. So it can happen, especially in high-frequency designs, that the gate sizing keeps increasing if the speed target is too aggressive.

The first electronic calculator to be built with large-scale integrated circuits (LSI), the Sharp QT-8D from 1969, used 4-phase logic, which was fabricated by Rockwell International because Japan did not yet have the LSI technology to do it domestically.{{Cite web |url=http://www.vintagecalculators.com/html/sharp_qt-8d.html|title = Sharp QT-8D |publisher=VintageCalculators}} 4-phase logic was also considered for use in the Intel 4004, but only Rockwell had the design tools and expertise to do large scale 4-phase ICs at that time so Intel settled on 2-phase dynamic logic instead. {{Cite web|url=http://www.intel4004.com/mrld.htm |title=The New Methodology for Random Logic Design Used in the 4004 and All the Early Intel Microprocessors: The Silicon Gate Design Methodology |work=The Intel 4004 Microprocessor and the Silicon Gate Technology }}

Evolution

With the advent of CMOS, the precharge transistor could be changed to be the complement of the logic transistor type, which allows the gate's output to charge quickly up to the high level of the clock line, thus improving the speed, signal swing, power consumption, and noise margin. This technique is used in domino logic.

References

Category:Logic families